A low power and low phase noise PLL frequency synthesizer for Ka-band application in 65 nm process

Abstract

This paper presents a fully integrated phase-locked loop (PLL) frequency synthesizer for Ka-band wireless communication application in standard 65nm CMOS process. Post-layout simulation shows that the voltage controlled oscillator (VCO) achieves a phase noise of −105dBc/Hz@1MHz offset with a tuning range of over 17%, and the PLL synthesizer provides output frequencies from 25.5 GHz to 30.3 GHz thanks to the self-biased buffer. Moreover, benefiting from the combination of current-mode-logic (CML) dividers and voltage-mode-logic (VML) dividers, the PLL consumes a total power dissipation of only 33.6mW with a single 1.2 V supply including all the buffers. And the PLL occupies an area of 0.86 mm × 0.65 mm with all the testing pads.