Low power design of variable centre frequency CMOS VCO

Abstract

This paper reports design of a voltage controlled oscillator (VCO) for low power consumption and generation of variable centre frequencies. The current starved technique is used for design of VCO. In normal current starved VCO circuits the centre frequency remains fixed, but here the circuit is designed for generating different centre frequencies, which makes the VCO more versatile. It can generate more frequencies with better resolution. The centre frequency and power dissipation both depend on the number of stages which is selectable. Power dissipation of VCO is estimated based on mathematical modelling and compared with simulation results. Extensive simulations along with performance evaluation of VCO is done to check output frequency and power dissipation. Best simulation results obtained on Tanner EDA tool show that centre frequency can be varied from 3.04 to 9.76 MHz through stage selection. Also, a reduction in power dissipation is obtained from 330 mW to 210 mW through stage selection.