Abstract

This paper presents an active microchannel neural interface (MNI) using seven stacked application specific integrated circuits (ASICs). The approach provides a solution to the present problem of interconnect density in three-dimensional (3-D) MNIs. The 4 mm2 ASIC is implemented in 0.35 μm high-voltage CMOS technology. Each ASIC is the base for seven microchannels each with three electrodes in a pseudo-tripolar arrangement. Multiplexing allows stimulating or recording from any one of 49 channels, across seven ASICs. Connections to the ASICs are made with a five-line parallel bus. Current controlled biphasic stimulation from 5 to 500 μA has been demonstrated with switching between channels and ASICs. The high-voltage technology gives a compliance of 40V for stimulation, appropriate for the high impedances within microchannels. High frequency biphasic stimulation, up to 40 kHz is achieved, suitable for reversible high frequency nerve blockades. Recording has been demonstrated with mV level signals; common-mode inputs are differentially distorted and limit the CMRR to 40 dB. The ASIC has been used in vitro in conjunction with an oversize (2mm diameter) microchannel in phosphate buffered saline, demonstrating attenuation of interference from outside the microchannel and tripolar recording of signals from within the microchannel. By using five-lines for 49 active microchannels the device overcomes limitations when connecting many electrodes in a 3-D miniaturized nerve interface.

Highlights

  • I NTERFACES with the nervous system have many clinical and investigative applications

  • This paper presents the design and test of an application specific integrated circuits (ASICs) for use in place of passive conductors in a microchannel neural interface (MNI) to solve problems with interconnect size in a 3-dimensional structure

  • This paper is an expansion of [35]. It provides a comprehensive description of the ASIC architecture including the biasing unit and the role of switch unit pairs in each mode, micrographs of manufacturing steps, ASIC ID setting for multi-ASIC multiplexing by laser ablation, measurements of biphasic current controlled stimulation, measurements of stimulation switching between ASICs, measurements of stimulation switching between channels on single ASICs, measurements of high frequency stimulation, results of biasing and recording across signal amplitudes and biasing setups, and tests using an in vitro microchannel demonstrating interference attenuation and tripolar recording

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Summary

INTRODUCTION

I NTERFACES with the nervous system have many clinical and investigative applications. Minimum “mini-nerve” diameter is limited to approximately 100 μm because smaller diameter microchannels become occluded with fibrotic tissue [23] This design increases signal amplitude by restricting space for extracellular current flow [24]. This paper is an expansion of [35] It provides a comprehensive description of the ASIC architecture including the biasing unit and the role of switch unit pairs in each mode, micrographs of manufacturing steps, ASIC ID setting for multi-ASIC multiplexing by laser ablation, measurements of biphasic current controlled stimulation, measurements of stimulation switching between ASICs, measurements of stimulation switching between channels on single ASICs, measurements of high frequency stimulation, results of biasing and recording across signal amplitudes and biasing setups, and tests using an in vitro microchannel demonstrating interference attenuation and tripolar recording.

Overall System
ASIC Design
Stacked ASIC Microchannel Neural Interface Assembly
Intermediate Hub
MEASUREMENTS
Power Consumption
Stimulation
Recording
In Vitro Microchannel Tests
DISCUSSION AND CONCLUSION

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