Mixed-signal Design Research Articles

A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis

Analog and mixed-signal (AMS) computer-aided design tools are of increasing interest owing to demand for the wide range of AMS circuit specifications in the modern system on a chip and faster time to market requirement. Traditionally, to accelerate the design process, the AMS system is decomposed into smaller components (called modules ) such that the complexity and evaluation of each module are more manageable. However, this decomposition poses an interface problem, where the module’s input-output states deviate from when combined to construct the AMS system, and thus degrades the system expected performance. In this article, we develop a tool module-linking-graph assisted hybrid parameter search engine with neural networks (MOHSENN) to overcome these obstacles. We propose a module-linking-graph that enforces equality of the modules’ interfaces during the parameter search process and apply surrogate modeling of the AMS circuit via neural networks. Further, we propose a hybrid search consisting of a global optimization with fast neural network models and a local optimization with accurate SPICE models to expedite the parameter search process while maintaining the accuracy. To validate the effectiveness of the proposed approach, we apply MOHSENN to design a successive approximation register analog-to-digital converter in 65-nm CMOS technology. This demonstrated that the search time improves by a factor of 5 and 700 compared to conventional hierarchical and flat design approaches, respectively, with improved performance.

Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation

For mixed-signal systems, identifying the analog and digital circuit blocks in the transistor-level netlist has many benefits for system analysis and verification. However, existing approaches still have difficulty handling large mixed-signal designs with millions of transistors, especially when multiple analog structure patterns are included. In this paper, we propose an efficient structure recognition methodology to support analyzing highly complex designs with various circuit structures and different devices. In order to tackle the complexity of real cases, a hierarchical partition-based analysis methodology and an encoding-based fast screening technique are proposed in this work. To correctly ascertain the boundary of analog and digital structures, we propose an enhanced direct current connection (DCC) partition method and combine it with the analog structure analysis flow. The non-transistor devices, such as resistors and capacitors, are also included in our recognition flow to improve the recognition capability and accuracy. As demonstrated with two industrial cases, the behavioral models generated from the structure recognition results do help to improve the efficiency of the AMS system verification.

Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review

Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications.

Characterization and hierarchical static timing analysis of mixed-signal design

As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.

Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration

Recent integration of Resistive Random Access Memory (RRAM) with standard CMOS has spurred exploration of high-density and low-power in-memory computing. RRAM arrays are being intensely investigated for analog-domain Vector Matrix Multiplication (VMM) and Neuromorphic Computing. However, to exploit the advantages of RRAM over other forms of nonvolatile memories, mixed-signal circuit designers need to accommodate their device nonidealities, and design circuits to translate high-level deep neural network algorithms to mixed-signal hardware. This brief reviews the field of neuromorphic computing using hybrid CMOS-RRAM circuits, associated circuit design challenges, and potential approaches for their mitigation, followed by benchmarking of recent demonstrations.

Design of low power fault tolerant flash ADC for instrumentation applications

Technological growth has remarkably put their efforts in making the electronic world a powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of transforming analog information into digital form. It is a necessary component in RF and Mixed signal designs. This paper suggests both neither compact NOR based CMOS Linear Tuneable Transconductance Element (NOR-LTE) Comparator and Dynamic Priority Encoder (DPE). The NOR-LTE comparator reduces the power utilization and offset error, which improves the Power Supply Rejection Ratio (PSRR) of an overall circuit design. Dynamic Priority Encoder curtails the transistor count prescribed for Flash ADC. The proposed Fault Tolerant Flash ADC (FT-FADC) framework is implemented using Tanner EDA with 0.25 ​ ​μm CMOS technology. The above suggested FT- FADC achieves 3.44-bit ENOB at 1.5 ​V supply for 500 ​MHz Resolution Bandwidth (RSB). Due to high sampling rate 1.3 ​GS/s it upgrades the throughput rate by 60% and reduces the utilization of power by 47%.

Robust H∞ performance for discrete time T-S fuzzy switched memristive stochasticneural networks with mixed time-varying delays

ABSTRACT In this paper, we study the robust H ∞ performance for discrete-time T-S fuzzy switched memristive stochastic neural networks with mixed time-varying delays and switching signal design. The neural network under consideration is subject to time-varying and norm bounded parameter uncertainties. Decomposing of the delay interval approach is employed in both the discrete delays and distributed delays. By constructing a proper Lyapunov-Krasovskii functional (LKF) with triple summation terms and using an improved summation inequality techniques. Sufficient conditions are derived in terms of linear matrix inequalities (LMIs) to guarantee the considered discrete-time neural networks to be exponentially stable. Finally, numerical examples with simulation results are given to illustrate the effectiveness of the developed theoretical results.

An Initiative Towards Analog And Mixed Signal Design - Prakalp

Abstract This paper presents a case study at School of Electronics and Communication, KLE-Tech which facilitated in preparing students ready for VLSI industry by bridging the gap between industry and institute. Collaboration between School of Electronics and Communication and Sankalp Semiconductors Pvt. Ltd., ventured as Prakalp program. In this program, the selection process of the interested students in the field of VLSI is through screening test. They are trained intensively by experts from industry and academia on fundamentals and advance courses of Analog and Mixed Signal VLSI to do the industry defined projects and experience research at the graduate level. Fundamental courses required for carrying out analog VLSI projects and research are covered as a part of professional core courses in the curriculum and to enhance this activity elective courses such as Analog Circuit Design followed by Physical Design-Analog are being conducted. Design, delivery and project based evaluation is by experts from Academia and Industry. Students are encouraged to submit their work to national conferences and contests. Sankalp and other VLSI companies recruit the best performing students

The University of Limerick Holds Oversampled Data Converter Design Course [Chapters

The University of Limerick Holds Oversampled Data Converter Design Course The Circuits and Systems Research Group (www.csrc.ie) of the Department of Electronics and Computer Engineering, University of Limerick (UL), Ireland (www.ul.ie), held its fifth annual two-day short-course “Selected Topics in Mixed-Signal IC Design” in Limerick on 24–25 June 2019.

Neuromorphic System for Spatial and Temporal Information Processing

Neuromorphic systems that learn and predict from streaming inputs hold significant promise in pervasive edge computing and its applications. In this paper, a neuromorphic system that processes spatio-temporal information on the edge is proposed. Algorithmically, the system is based on hierarchical temporal memory that inherently offers online learning, resiliency, and fault tolerance. Architecturally, it is a full custom mixed-signal design with an underlying digital communication scheme and analog computational modules. Therefore, the proposed system features reconfigurability, real-time processing, low power consumption, and low-latency processing. The proposed architecture is benchmarked to predict on real-world streaming data. The network's mean absolute percentage error on the mixed-signal system is 1.129X lower compared to its baseline algorithm model. This reduction can be attributed to device non-idealities and probabilistic formation of synaptic connections. We demonstrate that the combined effect of Hebbian learning and network sparsity also plays a major role in extending the overall network lifespan. We also illustrate that the system offers 3.46X reduction in latency and 77.02X reduction in power consumption when compared to a custom CMOS digital design implemented at the same technology node. By employing specific low power techniques, such as clock gating, we observe 161.37X reduction in power consumption.

A2Event: A Micro-Watt Programmable Frequency-Time Detector for Always-On Energy-Neutral Sensing

Internet of Things (IoT) sensors are becoming more and more intelligence and unobtrusive, surrounding us in everyday life. A key requirement for those devices is to be “always-on” performing “smart” detection to catch only the events of interest when they occur. A recent and trend is to design low power circuit to extract features close to the sensors without an analog-digital conversion. The goal is to achieve place-and-forget deployment with perpetual operation: this poses the challenge of achieving micro-watt power consumption of the always-on analog event detector and of harvesting energy from environmental sources, to supply the smart sensor. This paper presents A2Event (Analog to Event), a microwatt programmable pattern recognition circuit for analog sensors, with up to 128 simultaneous time-frequency features exploiting mixed-signal low power design, which is able to generate an event when a targeted pattern is recognized. Moreover, the paper proposes a self-sustaining always-on smart audio detector that combines A2Event with energy harvesting to detect events of interests perpetually. Experimental results show that A2Event consumes only 26.89 μW in always-on mode, during the time-frequency feature-extraction, while the whole system consumes only 63 μW during pattern recognition including the power for a commercial MEMS microphone and the energy harvesting subsystem. We demonstrate that the whole smart sensor operates perpetually when powered with a small form factor flexible photovoltaic panel in indoor lighting conditions, achieving a detection accuracy of 100% in the detection of two different audio streams.

A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration

This paper presents a ferroelectric FET (FeFET)-based processing-in-memory (PIM) architecture to accelerate the inference of deep neural networks (DNNs). We propose a digital in-memory vector-matrix multiplication (VMM) engine design utilizing the FeFET crossbar to enable bit-parallel computation and eliminate analog-to-digital conversion in prior mixed-signal PIM designs. A dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Simulations in 28-nm CMOS technology show $115\times $ and $6.3\times $ higher computing efficiency (GOPs/W) over desktop GPU (Nvidia GTX 1080Ti) and resistive random access memory (ReRAM)-based design, respectively.

Design of Low Power, High Gain Fully Differential Folded Cascode Operational Amplifier for Front End Read Out Circuits

The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.

Design and characterization of superconducting nanowire-based processors for acceleration of deep neural network training

Training of deep neural networks (DNNs) is a computationally intensive task and requires massive volumes of data transfer. Performing these operations with the conventional von Neumann architectures creates unmanageable time and power costs. Recent studies have shown that mixed-signal designs involving resistive crossbar architectures are capable of achieving acceleration factors as high as 30 000 × over the state of the art digital processors. These approaches involve utilization of non-volatile memory elements as local processors. However, no technology has been developed to-date that can satisfy the strict device requirements for the unit cell. This paper presents the superconducting nanowire-based processing element as a crosspoint device. The unit cell has many programmable non-volatile states that can be used to perform analog multiplication. Importantly, these states are intrinsically discrete due to quantization of flux, which provides symmetric switching characteristics. Operation of these devices in a crossbar is described and verified with electro-thermal circuit simulations. Finally, validation of the concept in an actual DNN training task is shown using an emulator.

Correction to “Evolution, Challenges and Attributes of Near Micron Sized TaN Resistors for Mixed Signal IC Applications From a Lithography Perspective” [Nov 18 460-466

The abstract in [1] is incorrect. The word “photograph” was used in error rather than the more correct, “photo.” The abstract should read: In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photo process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes.

An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification

Real number models, which are computationally efficient analog functional models, are now indispensable in verifying complex mixed-signal systems on chip (SoCs); yet, creating and validating these models remain difficult. To remove this problem, we created a framework for building analog functional model templates. Each template covers a class of circuits (e.g., oscillators or amplifiers) and can generate functional models for any implementation of this circuit class, regardless of pin configurations, circuit topologies, and process technologies/corners. This ability to cover many implementations with one template allows one to create a “standard model template” library that covers all the basic analog building blocks used in mixed-signal SoCs. Like a digital standard cell library, this template library only contains the low-level building blocks. Models for more complex systems, such as a phase-locked loop, are constructed using a number of these models. Our template library also contains validation routines for each of the models, measuring the key performance parameters of the modeled function. These routines can also be used to drive the circuit-level implementation of this function, making it easy to update the parameters of the functional models to match their circuit implementations. We demonstrate the utility of our template library on several mixed-signal IPs integrated into an SoC. Using the proposed framework, designers can easily generate a working model of an analog functional block in a second and thus construct a complete mixed-signal IP model for the design exploration in less than a couple of hours, while it typically needs a few days when the models are manually written. The regeneration of the models to reflect the behaviors of real implementations can be seamlessly done in less half a day from the same template library. In addition to the vast improvement in model creation speed, the generated model from the template library is less error-prone by archiving designer’s experience from previous mistakes to the template library.

Evolution, Challenges and Attributes of Near Micron Sized TaN Resistors for Mixed Signal IC Applications From a Lithography Perspective

The abstract in [1] is incorrect. The word “photograph” was used in error rather than the more correct, “photo.” The abstract should read: In this paper, the evolution of various lithographic processes aimed at fabricating robust tantalum nitride (TaN) resistors in GaAs-based BiFET and BiHEMT technologies are discussed in detail. Such approaches include the common image reverse photo process (via amine poisoning) using a positive tone resist, the use of a chemically amplified negative tone resist, and also straight patterning of a positive tone resist. The aforementioned approaches were found to have their own unique challenges as it applied to printing robust TaN-based resistors approaching nearly a micron in width which is needed for high density mixed signal designs. We will explore many of these challenges in detail for the various lithography schemes.

Design and implementation of reliable flash ADC for microwave applications

Analog to Digital Converter (ADC) is a necessary component of mixed signal designs. It converts the analog signal to the digital signal so that it is used as a bridge. This paper proposes R-Flash ADC (Reliable Flash ADC) which combines an area efficient multiplexer pass gate (MPG) encoding technique and low power ITIQ (Improved Threshold Inverter Quantization) comparator. The proposed Flash ADC is implemented using tanner EDA with 125 nm technology. R-Flash ADC reduces the number of transistors by 39% and reduces the power consumption by 59% with high resolution quality when compared to Mux TIQ ADC. The reliability analysis shows that the proposed R-Flash ADC has reliability of 95% and it overcomes the existing techniques as well.

A 0.6 V 117 nW high performance energy efficient system-on-chip (SoC) CMOS temperature sensor in 0.18 µm CMOS for aerospace applications

This research article presents and describes a novel design with improved performance low power consumption threshold voltage based CMOS thermal sensor for aerospace applications. The proposed temperature sensor utilizes the change in behavior of threshold voltage of MOSFET with variation in temperature. The challenge while designing the temperature sensor was to achieve the linearize output voltage with respect to change in temperature. Process corner analysis has been done to check the robustness of the circuit while performance analysis and sensitivity of the temperature sensor have been verified in the occurrence of parasitic. The proposed temperature sensor is featured with low power consumption, less power supply voltage utilization, high performance and sensitivity with inaccuracy as low as possible. The presented temperature sensor utilizes an active area of 18 µm × 9.85 µm with 117 nW power consumption. An improved linear performance with an inaccuracy of merely − 0.01 to + 0.47 °C over a wide temperature range of − 20 to + 120 °C is presented here. The sensitivity of proposed temperature sensor is found to be as high as 0.77 mV/°C. The proposed temperature sensor is realized and tested in Cadence virtuoso mixed signal design atmosphere using 0.18 µm CMOS technology and further investigated with support of tool from Mentor graphics. The engaged area of pad-limited chip is measured to be 0.96 mm2.

Focus on test, measurement, software, and instrumentation

Focus on test, measurement, software, and instrumentation