Single-event Transient Mitigation Research Articles

Mitigation of single-event transients in high-frequency analog circuits using choke inductors

Mitigation of single-event transients in high-frequency analog circuits using choke inductors

Novel layout technique for single-event transient mitigation by the groove structure

Based on the damage mechanism of single-event transient (SET) in a MOS device, a new irradiated reinforcement uniaxial strained Si Nano NMOSFET device is further proposed, and the new structure device has no effect on the electrical properties of its original structure. Moreover, the new reinforced device of groove structure can efficiently reduce not only charge collection but also SET pulse widths (WSET). Compared with the conventional NMOS and drain-wall structure, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in the effective area. Therefore, the successful development of the research results will play a positive role in promoting the theoretical and technological progress of high-performance radiation-resistant core electronic components and lay a foundation and create conditions for their application in space radiation and nuclear radiation.

Pulse quenching based radiation-hardened by design technique for analog single-event transient mitigation on an operational amplifier in 28 nm bulk CMOS process

In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

Cryogenic Characterization of RF Low-Noise Amplifiers Utilizing Inverse-Mode SiGe HBTs for Extreme Environment Applications

The cryogenic performance of radiation-hardened radio-frequency (RF) low-noise amplifiers (LNAs) is presented. The LNA, which was originally proposed for the mitigation of single-event transients (SETs) in a radiation environment, uses inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in its core cascode stages. In this prototype, the upper common-base SiGe HBT is configured in inverse mode for balanced RF performance and reduced SET sensitivity. In order to better exploit the inverse-mode LNAs in a variety of extreme-environment applications, the RF performance of the LNA was characterized using liquid nitrogen to evaluate cryogenic operation down to 78 K. While the SiGe LNA exhibits acceptable RF performance for all temperature conditions, there is a noticeable gain drop observed at 78 K compared to the conventional forward-mode design. This is attributed to the limited high-frequency performance of an inverse-mode SiGe HBT. As a guideline, compensation techniques, including layout modifications and profile optimization, are discussed for the mitigation of the observed gain degradation.

P-n-p-Based RF Switches for the Mitigation of Single-Event Transients in a Complementary SiGe BiCMOS Platform

The benefits of using p-n-p silicon–germanium (SiGe) heterojuction bipolar transistors (HBTs) in radio frequency (RF) circuits for the mitigation of single-event transients (SETs) have been investigated. As a representative circuit example, p-n-p SiGe-HBT RF single-pole single-throw (SPST) switches have been designed in a complementary SiGe BiCMOS platform. The fabricated p-n-p-based RF switches provide comparable RF performance to n-p-n-based switches. In terms of SET transient peaks and duration, the p-n-p SiGe HBT RF switches exhibit a significant reduction in SET sensitivity compared with their n-p-n counterparts. In the frequency domain, the p-n-p switches show fewer low-frequency spurs than that of the n-p-n switches. In addition, inverse-mode p-n-p SiGe HBT switches provide the best overall SET response among all RF SPST switches investigated.

Investigation of single-event transient mitigation via pulse quenching in logic circuits

A layout technique which can mitigate single-event effect via pulse quenching is tested in this paper. The new limitation of application of this layout technique is affirmed in 65nm technology. The layout design via pulse quenching has no effects in PMOS, but it can work in NMOS in basic logical circuits. Combinational logic circuits still can use this method to defense single-event effect.

On the Application of Inverse-Mode SiGe HBTs in RF Receivers for the Mitigation of Single-Event Transients

Best practice in mitigation strategies for single-event transients (SETs) in radio-frequency (RF) receiver modules is investigated using a variety of integrated receivers utilizing inverse-mode silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The receivers were designed and implemented in a 130-nm SiGe BiCMOS technology platform. In general, RF switches, low-noise amplifiers (LNAs), and downconversion mixers utilizing inverse-mode SiGe HBTs exhibit less susceptibility to SETs than conventional RF designs, in terms of transient peaks and duration, at the cost of RF performance. Under normal RF operation, the SET-hardened switch is mainly effective in peak reduction, while the LNA and the mixer exhibit reductions in transient peaks as well as transient duration.

The Use of Inverse-Mode SiGe HBTs as Active Gain Stages in Low-Noise Amplifiers for the Mitigation of Single-Event Transients

A cascode configuration with inverse-mode (IM) common-emitter silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is proposed for the mitigation of single-event transients (SETs) in low-noise amplifiers (LNAs). Conventionally, despite their SET-mitigation capability, IM SiGe HBTs have been considered to be unsuitable for active gain stages due to severe degradation in RF performance. However, with the benefits of aggressive technology scaling, the high frequency performance of IM SiGe HBTs has been significantly improved, thereby enabling them to be utilized in active gain stages with acceptable RF performance. The cascode with IM common-emitter and common-base SiGe HBTs is used for a 2.4 GHz prototype LNA and it achieves adequate RF gain (10 dB) and noise figure (1.9 dB). With regard to SET mitigation, a through-wafer two-photon absorption pulsed-laser experiment is conducted to test the efficacy of this radiation-hardening approach in an advanced 90 nm SiGe BiCMOS platform. The proposed IM-SiGe-HBT-based LNA exhibits 85% reduction in transient peaks compared to the conventional forward-mode cascode LNA.

An Investigation of the Use of Inverse-Mode SiGe HBTs as Switching Pairs for SET-Mitigated RF Mixers

The capability of inverse-mode (IM) silicon- germanium (SiGe) heterojunction bipolar transistors (HBTs) for the mitigation of single-event transients (SETs) under large-signal operation was investigated in an RF down-conversion single- balanced mixer using a through-wafer, two-photon absorption pulsed-laser beam experiment and TCAD heavy-ion simulations. The IM SiGe HBTs replace conventional forward-mode (FM) SiGe HBTs in the differential pair, which provides full current steering for frequency mixing operation. Under steady-state conditions, the IM SiGe HBT differential pair exhibits smaller transient peaks with shorter durations compared to the FM SiGe HBTs. In addition, under the injection of a local oscillator (LO) signal with large swing, the IM SiGe HBTs show faster recovery (50% reduction in the best case) from the impact of SETs. In the frequency domain, it is observed that IM SiGe HBTs produce less distortion at the output for an intermediate frequency below 1 GHz. Based on the performance comparison between FM and IM SiGe HBT down-conversion mixers, system design guidelines to compensate the noise figure degradation associated with using IM SiGe HBTs are discussed.

Optimization of SiGe HBT RF Switches for Single-Event Transient Mitigation

Optimization of SiGe HBT RF Switches for Single-Event Transient Mitigation

Mirror image: newfangled cell-level layout technique for single-event transient mitigation

Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cell-circuit module to mitigate single event transient (SET) sensitivity. The mirror image (MI) technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twin-well bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25 %, and can mitigate the SET pulse width from the posterior-stage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits.

Novel N-hit single event transient mitigation technique via open guard transistor in 65nm bulk CMOS process

In this paper, we proposed a new n-channel MOS single event transient (SET) mitigation technique, which is called the open guard transistor (OGT) technique. This hardening scheme is compared with several classical n-channel MOS hardening structures through 3-D TCAD simulations. The results show that this scheme presents about 35% improvements over the unhardened scheme for mitigating the SET pulse, and its upgrade, the 2-fringe scheme, takes on even more than 50% improvements over the unhardened one. This makes significant sense for the semi-conductor device reliability.

Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation

In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source isolation is studied by way of technology-computer-aided-design numerical simulations. The source-isolation layout design methodology is thoroughly discussed for the combinational standard cell. Based on a 90-nm twin-well CMOS technology, the simulation results indicate that the proposed “radiation hardened by design” (RHBD) technique can significantly reduce SET pulsewidth. The effects of the ion strike angles and strike locations on this hardened technique are also studied, and the area penalty is also discussed. When we combine the layout technique that utilizes the quenching effect with the proposed source-isolation layout technique, the RHBD standard-cell library can be further exploited for additional P-hit SET mitigation in the spaceborne integrated-circuit design.