MISFET Devices Research Articles

β-Ga2O3 lateral transistors with high aspect ratio fin-shape channels

We report on β-Ga2O3 fin-shape transistors in a lateral geometry. The fin channel devices were fabricated on MOCVD-grown lightly Si-doped (010) β-Ga2O3 films. A hot phosphoric acid etch was used to remove dry etch damage and for the fabrication of sub-micron channels. Lateral fin-channel MESFETs and MISFETs with different fin widths were systematically studied. Electron conduction in the MISFET devices was found to be dominated by electron accumulation at the dielectric/semiconductor interface. In addition, the MISFETs showed higher drain-induced barrier lowering as compared to the MESFET devices. Comparison of the MISFETs with different fin widths suggested the importance of thin fin channels for better gate control and higher breakdown voltages.

Metal–insulator–semiconductor field-effect transistors (MISFETs) using p-type SnS and nanometer-thick Al2S3 layers

SnS based MISFET devices exhibit a high turn-on voltage of +5.13 V and rectification factor of 1383@+6 V.

Fundamental Characteristics of SiC MIS Structure with Al<sub>2</sub>O<sub>3</sub> as Gate Dielectric

SiC MIS structure with ultra-thin Al2O3as gate dielectric deposited by Atomic Layer Deposition(ALD) on epitaxial layer of 4H-SiC(0001)80N-/N+ substrate is fabricated. The experimental results indicate that the prepared ultra Al2O3gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25MV/cm, excellent interface properties(2×1013cm-2•eV-1) and low gate-leakage current (IG=1×10-3A/㎝-2@EOX=8MV/cm). Analysis of current conduction mechanism in deposited Al2O3gate dielectric has also been systematically performed. The confirmed conduction mechanisms consisted of FP emission, FN tunneling, DT and Schottky emission. And the dominance of these current conduction mechanisms depended on applied electrical field, When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3is 1.4eV, which can meet the requirement of SiC MISFET devices.

Fundamental characteristics of SiC MIS structure with Al<sub>2</sub>O<sub>3</sub> as gate dielectric

SiC MIS structure with ultra-thin Al2O3 as gate dielectric deposited by atomic layer deposition (ALD) on epitaxial layer of 4H-SiC(0001)8°N-/N+ substrate is fabricated. The microstructure and electrical characteristics analysis on the film and Al2O3/SiC interface has shown that Al2O3 deposited has a good bulk characteristics and a good quality between Al2O3 and SiC. The breakdown electrical field of Al2O3 film is 25 MV/cm; the MIS capacitor has a fairly low gate leakage current (current density of 1×10-3A/cm-2 with a electric field of 8 MV/cm) under acceptable interface effective charge (2×1013 cm-2). Current-voltage measurement and analysis has shown that when the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirement of SiC MISFET devices. Besides this, the gate leakage current is co-influenced by both of Frenkel-Poole mechanism and Schottky emission.

Modeling the Carrier Mobility in Nanowire Channel FET

AbstractWe report on the extraction of carrier type, and mobility in semiconductor nanowires by adopting experimental nanowire field-effect transistor device data to a long channel MISFET device model. Numerous field-effect transistors were fabricated using n-InAs nanowires of a diameter of 50 nm as a channel. The I-V data of devices were analyzed at low to medium drain current in order to reduce the effect of extrinsic resistances. The gate capacitance is determined by an electro-static field simulation tool. The carrier mobility remains as the only parameter to fit experimental to modeled device data. The electron mobility in n-InAs nanowires is evaluated to µ = 13,000 cm2/Vs while for comparison n-ZnO nanowires exhibit a mobility of 800 cm2/Vs.

Power and Linearity Characteristics of GaN MISFETs on Sapphire Substrate

The improvement of device performance arising from the adoption of a MIS gate structure in GaN field-effect transistor (FET) is presented. GaN MISFET/MESFET devices were fabricated on sapphire substrate with and without the insertion of a thin SiN layer on device surface. The MISFET device showed improved device characteristic due to significant reduction in device gate leakage with respect to the standard MESFET structure. Measured power and linearity performance showed promising results. Under single-tone testing at 4 GHz, device yielded saturated output power 6.2 W/mm with 55% peak power added efficiency. When tested with two-tone signal device maintained a carrier to third order intermodulation ratio of 30 dBc up to power levels of 1.8 W/mm with 40% power added efficiency.

High Performance HFET Devices on Sapphire and SiC: Passivation with AlN

ABSTRACTAlGaN/GaN two dimensional electron gas (2DEG) heterostructures were grown by ammonia-MBE on sapphire and SiC substrates. Devices fabricated from these optimized HFET layers, with optically defined gates showed excellent characteristics, e.g. a maximum drain current density of 1.3 A/mm, maximum transconductance of 220 mS/mm, fT of 15.6 GHz and fMAX of 58.1 GHz was measured for devices with 0.9 μm gate length and 40 μm gate width. Shorter gate length devices exhibited higher frequency responses: fT of 68 GHz and fMAX of 125 GHz for 0.25 μm gate length and fT of 103 GHz and fMAX of 170 GHz for 0.15 μm gate length. However, these devices showed “current collapse” when subjected to load pull measurements. Current collapse was also observed in sequentially repeated DC measurements in the dark, both on sapphire and SiC substrates, although the degree of collapse varied greatly from one wafer to another. One method of reducing the current collapse was to apply a thin (100 - 6000 Å) magnetron sputtered AlN passivation layer (over the gates) or a 500 Å layer under the gates so that MISFET devices were obtained. The electrical characteristics of the passivated and unpassivated devices are discussed.

A quasianalytical model for LT–GaAs and LT–Al0.3Ga0.7As MISFET devices

This paper describes a quasianalytical model for the calculation of the current–voltage characteristics of LT–GaAs and LT–Al0.3Ga0.7As MISFET devices. The model is derived from basic semiconductor charge analysis. Poisson's equation, the current continuity equation, and the Chang–Fetterman velocity-field equations have been solved analytically. When the devices are operating in the linear region and the knee region, the one-dimensional Poisson equation is considered. When the devices are in the saturation regime, the two-dimensional Poisson equation is solved analytically. The resulting output current–voltage characteristics are in good agreement with experimental data. This model has been used to predict the RF performance and RF power capability of these MISFETs. © 2000 John Wiley & Sons, Inc. Microwave Opt Technol Lett 27: 61–66, 2000.

Thermal stability of MISFET with low-temp molecular-beam epitaxy-grown GaAs and Al/sub 0.3/Ga/sub 0.7/As gate ins

GaAs and Al/sub 0.3/Ga/sub 0.7/As epilayers grown at LT by MBE were used as insulators in the fabrication of MISFET devices. Parametric changes were used to evaluate the thermal stability of MISFET, to identify failure mechanisms and validate the reliability of these devices. The LT-Al/sub 0.3/Ga/sub 0.7/As MISFET showed superior thermal stability. The degradation in the performance of MISFET with 1000 /spl Aring/ thick LT-GaAs gate insulator was worse than those of the MESFET. On the other hand, MISFET with 250 /spl Aring/ thick LT-GaAs gate insulators exhibited stable characteristics with thermal stressing, LF (low frequency) noise studies on the TLM structures of MISFET layers exhibited 1/f noise in the LT-Al/sub 0.3/Ga/sub 0.7/As samples and 250 /spl Aring/ LT-GaAs samples; whereas the 1000 /spl Aring/ thick LT-GaAs samples exhibited 1/f/sup 3/2/ noise, which was attributed to: (i) the thermal noise generated at the interface of the insulator, and (ii) the active layer due to the outdiffused metallic arsenic. Reverse gate-drain current degradation experiments were carried out at 120/spl deg/C, 160/spl deg/C, 200/spl deg/C, and 240/spl deg/C. Transconductance frequency dispersion studies were carried out before and after thermal stress on these MISFET. The transconductance of MISFET with 1000 /spl Aring/ LT-GaAs gate insulators was degraded by 40% at 100 kHz after thermal stress. The rest of the samples exhibited stable characteristics. These results indicate that composition changes had occurred at the interface in thicker LT-GaAs MISFET structures. Thinner LT-layers are ideal for achieving higher transconductance and better thermal stability without sacrificing the power capability of MISFET.

A quasianalytical model for LT-GaAs and LT-Al0.3Ga0.7As MISFET devices

This paper describes a quasianalytical model for the calculation of the current–voltage characteristics of LT–GaAs and LT–Al0.3Ga0.7As MISFET devices. The model is derived from basic semiconductor charge analysis. Poisson's equation, the current continuity equation, and the Chang–Fetterman velocity-field equations have been solved analytically. When the devices are operating in the linear region and the knee region, the one-dimensional Poisson equation is considered. When the devices are in the saturation regime, the two-dimensional Poisson equation is solved analytically. The resulting output current–voltage characteristics are in good agreement with experimental data. This model has been used to predict the RF performance and RF power capability of these MISFETs. © 2000 John Wiley & Sons, Inc. Microwave Opt Technol Lett 27: 61–66, 2000.

Transient current spectroscopy and frequency dispersion studies of low temperature GaAs and Al0.3Ga0.7As metal-insulator-semiconductor diodes

Low temperature (LT)-grown GaAs and Al0.3Ga0.7As metal-insulator-n+-GaAs (MIN) diodes have been fabricated and their electrical properties analyzed. Studies were carried out to evaluate the interfacial quality of the LT layer and the underlying n+-GaAs layer using transient current spectroscopy (TCS) and capacitance-frequency (C-f) characterization. TCS studies on LT-GaAs revealed a high concentration of a continuum of states anda dominant electron trap with an activation energy of 0.52eV. In LT-Al0.3Ga0.7As, a shallow trap at 0.36eV and two deep level traps at 0.85eV and 1.12eV were observed. Frequency dispersion was observed to be less for LT-GaAs samples with an AlAs barrier layer than without an AlAs barrier layer. However, LT-Al0.3Ga0.7As MIN diodes displayed a smaller frequency dispersion than LT-GaAs MIN diodes. Upon further investigation into MISFET devices, it was found that LT-Al0.3Ga0.7As MISFET devices had better transconductance frequency dispersion characteristics than LT-GaAs MISFET devices did.

Low frequency noise analysis of LT-GaAs and LT-Al 0.3 Ga 0.7 AsMISFET active layers

Noise spectroscopy has been used to assess the quality of the active layers of LT-GaAs and LT-Al0.3Ga0.7As MISFET devices using transmission line model structures. Noise spectra were studied as a function of insulator thickness. LT-Al0.3Ga0.7As samples and a 500 A thick LT-GaAs sample exhibited 1/f noise. The noise parameter αlatt was found to be of the order 10–4 for these samples. 2000 A LT-GaAs samples exhibited 1/f3/2 noise with 500 Hz corner frequency.

Characteristics of GaAs MISFET devices using low-temperature-grownAl 0.3 Ga 0.7 As as gate insulator

Al0.3Ga0.7As epilayers grown at low-temperature (LT) by molecular beam epitaxy (MBE) were used as insulators in the fabrication of MISFET devices. An LT-Al0.3Ga0.7As MISFET, having a gate length of 2 µm, exhibited a transconductance of 161 mS/mm, an IDSS of 320 mA/mm and a maximum drain voltage of 44.7 V, resulting in an I-V product of 1.65 W/mm; it displayed improved frequency dispersion characteristics over that of an LT-GaAs MISFET.

Ultra-low conductivity through insulating self-assembled organic monolayers

We demonstrate that monolayers made of organic molecules (long chain hydrocarbons) as thin as to 1.9 nm form high performance electrically insulating barriers. Leakage current densities of the order of 10 −8 to 10 −7 A/cm 2 have been obtained. The energy barrier height to electron is so high (3.6 eV) that the tunnelling current through these monolayers is negligible. These properties put such ultra-thin organic monolayers on a par with 4 to 5 nm thick silicon dioxide, and enable us to envision possible applications in sub-0.1 μm channel length MISFET devices.

Synthesis of polyenes with chain-end mesogens via living ring-opening metathesis polymerization

The incorporation of mesogenic (liquid-crystalline) chain-end functionalities in polyacetylene (PA) can be achieved using the ‘Durham route’ and ‘Schrock-type’ well defined metal alkylidene initiators. These chain-end groups were designed to nucleate the self-organization of the polyenes in thin films prepared by spin coating of the precursor polymer onto MISFET device structures, since improvements of carrier mobility and conductivity are expected in well ordered materials.

Fabrication and electrical characterization of InGaAs MISFET using ultrathin Si interface control layer

AbstractA recess gate depletion‐type InGaAs MISFET has been fabricated by using a thick photo‐CVD SiO2 outer layer and on ultrathin MBE Si interface control layer (Si ICL) after HF treatment of air‐exposed InGaAs surface treated by HF. After optimum annealing of the MISFET at 350°C in hydrogen atmosphere for 1 hr, a significant increase of the transconductance was obtained and with a very stable drain current. Maximum effective mobility of 3850 cm2/V.s and a transconductance of 61 mS/mm for a gate length 6 μm were achieved.Based on the observed dependence of gate length on the transconductance, it is found that transconductance as much as 250 mS/mm can be expected for 1 μm gate length even after considering the velocity saturation effect. A drain current drift was controlled below 5 percent after 104 s after a gate step voltage was applied.The performance obtained in the present study is comparable to that of photo‐CVD SiO2/Si ICL/InGaAs MISFET fabricated in an in‐line process in ultrahigh vacuum. the result clearly demonstrates that an HF treatment of air‐exposed InGaAs surface is useful for a MISFET device process.

Drift effects in transition metal gate MOS and MISFETs

The types of drift exhibited by palladium gate MOS and MISFET devices are examined and described in this paper. The drift prior to exposure of the devices to hydrogen (baseline drift) can be separated into two distinct types. The first of these is a field inversion effect caused by adsorption of moisture onto the device whilst it is cold creating an inversion layer under the field oxide, followed by the removal of this moisture during operation of the device at an elevated temperature. This drift effect was seen to degrade the gas sensitivity of the devices. The second drift effect is due to the drift of mobile ions in the gate oxide. This process causes the baseline to drift but does not alter the gas sensitivity of the device. Methods of reducing or circumventing these drift effects are described. The drift of signal of palladium gate MOS and MISFETs during exposure to hydrogen gas is also described. Palladium gate MOSFETs are found to have larger signals and greatly increased drift compared to palladium gate MISFET devices. Furthermore, this drift is seen to be greatly dependent on the operating temperature of the device with the minimum drift occurring at a temperature of 150 °C. It is concluded that a large portion of the signal observed for palladium gate MOSFET devices is due to hydrogen related species drifting in the gate oxide.

Optimization of the InP/SiO2 interface treatment by (NH4)2Sx for the InP MISFET fabrication technology

In this paper, the InP surface sulfidation by (NH4)2S or (NH4)2Sx solutions is investigated in order to reduce the long-term drain-current-drift of MISFET devices and the interface state density at the InP/SiO2 interface. In order to ensure good reproducibility of this treatment, a full chemical characterization of the ammonium sulfide solutions is proposed. After surface sulfidation, an annealing is done in the photo-CVD chamber before depositing the insulator: at 350 °C the initial InPS4 layer is transformed into a stable In2S3 phase without degradation of the P/In ratio. Thanks to this InP surface processing, the 1 MHz and 10 kHz C(V) characteristics of MIS diodes exhibit a deep depletion regime, Nss = 2 × 1010 eV−1 cm−2, and very little frequency dispersion. These results are very encouraging for the MISFET fabrication process.

Progress in InP MISFET Devices

Recent advances in InP MISFET technology are reviewed in this paper. A significant improvement in the interface properties of insulator-semiconductor system has been shown to result through the selection of insulators compatible with InP. Tho processing conditions are also very important for obtaining good dielectric films with low interface state density for successful operation of these devices. Among the dielectrics yielding the best result are P-doped SiO2 and BN films. A new deposition technique of high temperature insulator like BN using a pulsed ruby laser has been discussed. This technique avoids substrate heating during deposition and consequently reduces P-outdiffusioin from InP surface.

A comprehensive analytical model for III-V compound MISFET's

A one-dimensional analytical model for III-V compound deep-depletion-mode MISFET's is developed. The model calculates transconductance, drain resistance, and gate capacitance beyond current saturation where these devices are normally operated-a regime not treated by other MISFET models. It is shown that insulator thicknesses less than 50 nm and surface state densities less than 1 × 1012eV-1. cm-2will be required for optimum MISFET devices. In a comparison of the expected performance differences between GaAs, InP, and InGaAs FET devices with similar geometries, it is shown that InP and InGaAs MISFET's will have lower gate capacitance, a greater cut-off frequency, and up to 2-dB improvement in minimum noise figure compared with a GaAs MESFET. Device characteristics predicted by this model agree with measured values to an accuracy of ±20 percent, which is well within the accuracy with which the modeled input parameters can be measured. This represents a factor of two improvement in accuracy when compared to other MISFET models. The model predicts the characteristics expected for a MESFET device in the limit of zero insulator thickness.