Minimum Chip Area Research Articles

A Floorplanning Algorithm with Minimum Total Length Wires

A floorplan is employed to represent the placement of modules in VLSI design. Floorplanning is a key step in the design of VLSI systems because it provides the first estimates of performance and cost including placement and routing. In this paper, we show an algorithm1 for initial global routing by the single-sequence (SS). The aim of our algorithm is to get a minimum chip area and the shortest total length of wires where the longest (critical) wire in every net is reduced to a minimum. The experimental results show that the design of placement and routing in floorplanning can be considered simultaneously by our algorithm, the efficiency of automatic layout in VLSI can be raised.

A Highly Reconfigurable Low-Power CMOS Directional Coupler

This paper presents a highly reconfigurable, low-power, and compact directional coupler. The coupler uses varactors and novel active inductors to achieve wide tuning ranges of operating frequencies and coupling coefficients. The use of a low-pass circuit architecture with only two inductors minimizes chip area, power consumption, and noise. The coupler is implemented in a 0.13-μm CMOS process. It occupies an area of 350 μm× 340 μm and consumes 40 mW or less power. The obtained 1-dB compression point is -3.2 dBm, and the measured noise figure is ~ 23 dB. These parameters compare favorably with previously published reconfigurable couplers. The measured coupling coefficient can be tuned from 1.3 to 9.0 dB at 4 GHz with 32 dB or better isolation and 15 dB or better return loss. The operating center frequency can be tuned from 2.0 to 6.0 GHz for a nominal 3-dB operation. These results agree with theoretical predictions and simulations reasonably well.

Look-Up Table Based Implementations of SHA-3 Finalists: JH, Keccak and Skein

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

A Compact W-Band CMOS Power Amplifier With Gain Boosting and Short-Circuited Stub Matching for High Power and High Efficiency Operation

Using cascode cell, inductance gain boosting and source degeneration techniques in 90 nm CMOS process, a two-stage power amplifier operating at 80 GHz with a minimum chip area of 0.35 mm2 demonstrates gain of 18 dB, linear output power of 10.8 dBm, saturated power of 13.3 dBm, and PAE greater than 11.8% when the amplifier is biased at Vd = 3 V and Vg = 1 V.

Compact quadrature receiver for 24 GHz radar applications in 0.13 [micro sign]m CMOS

A compact low-noise quadrature receiver for 24 GHz ISM applications in 0.13 µm CMOS technology is presented. The chip offers a conversion gain of 18 dB and a noise figure of 5 dB. The differential circuit consumes only 24 mW from a single 1.5 V supply. The low-noise amplifier, two mixers and on-chip quadrature generation are integrated on a minimal chip area of 0.48 mm2 including pads.

Temperature-aware floorplanning via geometric programming

With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 ∘C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 ∘C to 10 ∘C, where the minimized chip area is about 700 mm 2. For the case of MCNC ami49, the maximum temperature reduction is 60 ∘C (i.e., its reduction is from 65 ∘C to 5 ∘C) with a minimal chip area of 2500 mm 2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature- and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 μm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm2 consumes 16 μW at 8 kS/s and 2.5 V.

A Multiband Inductor-Reuse CMOS Low-Noise Amplifier

This paper presents the design and implementation of a new multiband, multistandard CMOS low-noise amplifier (LNA) that reuses inductors for different frequency bands to minimize chip area. The idea is to adaptively reconfigure a CMOS transistor in either common source or common gate configuration to achieve narrow-band (NB) or wide-band (WB) input matching, respectively, while conveniently reusing input and load inductors for both bands. This architecture is suitable for 802.11 a/b/g and Public Safety Broadband (PSB) applications, where the NB configuration covers wireless local area network (WLAN) 802.11 b/g, while the WB configuration accommodates the PSB at 4.9 GHz and WLAN 802.11 a. Two versions of the proposed idea, a tapped-capacitor and a tapped-inductor input-matched LNA, have each been designed and fabricated in 0.13-mum CMOS and measurement results are demonstrated.

An optimal structure for implementation of digital filters

In this paper, different structures for an elliptic filter with fixed-point arithmetic are implemented and compared. The filter must be quantized for hardware implementation. This quantization is done in two steps. First the coefficients of the filter are quantized and then the minimum required accuracy of the internal nodes is determined. According to the simulation results, lattice and DFII-parallel structures have minimal sensitivity to coefficient quantization. Also, the chip areas (i.e. gate counts)of different structures are computed. We show that overall, the DFI-parallel structure is the optimal structure for hardware implementation and requires minimal chip area at the needed precision.

A 10b 100 MS/s 1.4 mm256 mW 0.18 m CMOS A/D Converter with 3-D Fully Symmetrical Capacitors

This work proposes a 10b 100 MS/s 1.4 mm 2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at lOb accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 μm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.

Implementation of High-Coupling and Broadband Transformer in RFCMOS Technology

This paper proposes a structure for transformer with high-coupling, broadband, and small chip area characteristics using current silicon-based technology. The proposed device has tight coupling (k=0.92), wide bandwidth (f/sub SR/=30.8 GHz), and minimum chip area (OD=140 /spl mu/m). Furthermore, the analytical formula for calculating mutual inductance is derived in this study; experimental results indicate that the analytical formula is feasible. The proposed transformer will be useful in designing high-performance RF integrated circuits for wireless applications.

Dual-Band Mixer Design

This paper presents a dual-band mixer equipped with a dual-band load using current combine technique to minimize chip area by sharing inductors for each frequency band. A systematic design methodology for the current combine load based on parasitic effect considerations is also developed. By following the proposed design procedure, the load inductance and combine capacitance for the dual-band mixer can be easily determined. A 2.4/5.2-GHz CMOS mixer design has been implemented to demonstrate the feasibility of the design technique.

High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers

This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visible to the rest of the DDFS design and can be updated less frequently, which motivated the development of new accumulator designs. Without performance degradation, the proposed designs relieve constraints in implementation, and hence they can be employed for GHz-range DDFS, reduce power consumption up to 82% compared to standard accumulator design, and minimize chip area. For further power reduction, the proposed designs place the phase modulation adder at the front of the accumulator.

Prospects for terabit-scale nanoelectronic memories

We have calculated the minimum chip area overhead, and hence the bit densityreduction, that may be achieved by memory array reconfiguration (bad bit exclusion),combined with error correction code techniques, in prospective terabit-scale hybridsemiconductor/nanodevice memories, as a function of the nanodevice fabrication yield andthe micro-to-nano pitch ratio. The results show that by using the best (but hardlypracticable) reconfiguration and block size optimization, hybrid memories with a pitchratio of 10 may overcome purely semiconductor memories in useful bit density if thefraction of bad nanodevices is below , while in order to get an order-of-magnitude advantage in density, the number of baddevices has to be decreased to . For the simple ‘Repair Most’ technique of bad bit exclusion, complemented withthe Hamming-code error correction, these numbers are close to 2% and 0.1%,respectively. When applied to purely semiconductor memories, the same techniqueallows us to reduce the chip area ‘swelling’ to just 40% at as many as 0.1% of baddevices. We have also estimated the power and speed of the hybrid memoriesand have found that, at a reasonable choice of nanodevice resistance, both theadditional power and speed loss due to the nanodevice subsystem may be negligible.

Trees, slices, and wheels: On the floorplan area minimization problem

AbstractHierarchical approaches to floorplan design usually use trees to represent hierarchical floorplans, defining topological relations between a set of components to be placed on a (circuit) board. This placement is then optimized to minimize chip area, perimeter, or other such cost measurements. This work places the problem of minimizing hierarchical floorplans of order k within the appropriate theoretical framework and presents an algorithm that uses exclusively the k‐ary representation tree to determine the best or minimal solution to a conflicting bicriteria problem. The algorithm does not need predefined partitioning schemes and determines the orientation of each individual component. It can deal both with five‐module wheels, as well as slices, and can handle an arbitrary number of realizations for each individual component. © 2003 Wiley Periodicals, Inc.

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against Vdd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.

A CMOS clock and data recovery circuit for intraocular microsystems.

This paper presents the implementation of a clock and data recovery circuit (CDR) for intraocular microsystems. The CDR was designed to minimize chip area and power consumption and to recover the clock and data signals from the incoming data stream. Since the CDR has been designed without any external components it is well suited for being integrated in an intraocular microsystem. Simulation results show that this CDR works with power dissipation of less than 2.4 mW with a single 3.3 V power supply. The simulations are based on a 0.6 micron n-well CMOS single-polysilicon, three-metal technology.

On-chip I/sub DDQ/ testing in the AE11 fail-stop controller

Targeted for safety-critical applications, this microcontroller replaces the classic two-controller safety structure with a single controller containing various online fault detection measures. To minimize chip area without reducing safety, the developers incorporated a combination of concurrent checking, BIST, and I/sub DDQ/ testing-and considerably extended the standard cell-based design flow.

STATE ENCODING OF FINITE STATE MACHINES FOR LOW POWER DESIGN

We address the problem of state encoding for synchronous finite state machines (FSMs), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor to power dissipation. In this work, we define a function λ for automatic tradeoff between switching activity and area that contribute to power dissipation. λ is used in determining the encoding affinity between states and is observed to be related to the number of states of an FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. The proposed approach does not require any change in the functional specification of the state machine and can be easily incorporated in present design flow. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented. A simple function for λ is provided, and it is shown to be robust in finding low-power state encodings.

A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 /spl mu/m single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm/sup 2/ for the digital PLL and 0.44 mm/sup 2/ for the analog PLL. It can handle an input data rate up to 280 Mb/s.