Minimal Hardware Research Articles

Ηand dexterities assessment in stroke patients based on augmented reality and machine learning through a box and block test

A popular and widely suggested measure for assessing unilateral hand motor skills in stroke patients is the box and block test (BBT). Our study aimed to create an augmented reality enhanced version of the BBT (AR-BBT) and evaluate its correlation to the original BBT for stroke patients. Following G-power analysis, clinical examination, and inclusion–exclusion criteria, 31 stroke patients were included in this study. AR-BBT was developed using the Open Source Computer Vision Library (OpenCV). The MediaPipe's hand tracking library uses a palm and a hand landmark machine learning model to detect and track hands. A computer and a depth camera were employed in the clinical evaluation of AR-BBT following the principles of traditional BBT. A strong correlation was achieved between the number of blocks moved in the BBT and the AR-BBT on the hemiplegic side (Pearson correlation = 0.918) and a positive statistically significant correlation (p = 0.000008). The conventional BBT is currently the preferred assessment method. However, our approach offers an advantage, as it suggests that an AR-BBT solution could remotely monitor the assessment of a home-based rehabilitation program and provide additional hand kinematic information for hand dexterities in AR environment conditions. Furthermore, it employs minimal hardware equipment.

SHREG: Mitigating register redundancy in GPUs

Graphics Processing Units (GPUs) have become dominant accelerators for Machine Learning (ML) and High-Performance Computing (HPC) applications due to their massive parallelism capabilities, through the utilization of general matrix-to-matrix multiplication (GEMM) kernels. However, GEMM kernels often suffer from duplicated memory requests, mainly caused by matrix tiling used for handling large matrices. While GPUs have adopted programmable shared memory to mitigate this issue by preserving frequently reused data in shared memory, GEMM still introduces duplication in register files. Our observations show that the matrix tiling issues memory requests to the same shared memory address for neighboring threads, and this results in a substantial increase in the number of duplicated data in the register files. Such duplication degrades GPU performance by limiting warp-level parallelism due to the register shortage and redundant memory requests to shared memory. We find that the data duplication can be categorized into two types that occur with fixed patterns during the matrix tiling. Based on these observations, we introduce SHREG, an architecture design that enables different threads to share registers for overlapped data from shared memory, effectively reducing duplicated data within the register files. By leveraging the duplication patterns, SHREG utilizes register sharing and improves performance with minimal hardware overhead. Our evaluation shows that SHREG improves performance by 31.4% on various ML applications over the baseline GPU.

Differential optical transfer function (dOTF) broad-spectrum wavefront sensing using integral field unit spectroscopy

Context. Detecting and characterizing Earth-like exoplanets is a critical scientific goal for the next generation of telescopes. However, current direct imaging instruments are hindered by evolving noncommon path aberrations (NCPAs), which lead to persistent speckles in the images. The differential optical transfer function (dOTF) is an image-based, noniterative, and model-independent wavefront sensor that combines differential images to estimate the complex field of the pupil. Aims. Given the objective of spectrally characterizing exoplanets to discern their composition and potentially detect biosignatures, we aim to explore the integration of the dOTF sensing method with an integral field unit (IFU) spectrograph. An IFU spectrograph generates a spectral data cube that contains diverse spectral information within a single dataset. Combining these two concepts is expected to improve the efficiency with which NCPAs can be spectrally measured and characterized. Methods. This Letter presents an implementation strategy for integrating dOTF and IFU spectroscopy data, enabling estimations of the electric field at various wavelengths simultaneously. Results. This method is specifically optimized to provide the most effective combination with minimal hardware requirements. It involves the use of multiple simultaneous deformable mirror actuator displacements in conjunction with an adapted Lyot stop employing a circular variable filter. Conclusions. The dOTF wavefront sensor coupled with an IFU spectrograph promises to be rapid and efficient, capable of measuring NCPAs across the entire spectrum provided by the spectrograph. Because the combination of dOTF and IFU spectroscopy is immediately applicable, it is of potential interest for various present-day on-sky instruments, as well as future IFU-based instruments coupled to the next generation of extremely large telescopes (ELTs).

An inspired chaos-based estimation-theory optimization for low-density parity-check (LDPC) code decoding

Optimization techniques have emerged as powerful tools for solving complex engineering problems in real-time applications, surpassing traditional heuristic methods. This paper introduces a novel chaos optimization algorithm that integrates the bisection search method to enhance the convergence ability, solution accuracy, and search speed of conventional optimization problems. The proposed algorithm is applied to the design and analysis of a reduced complexity decoding scheme using Low-Density Parity-Check (LDPC) codes. By leveraging the Linear Minimum Mean Square Error (LMMSE) estimation criterion, the proposed method approximates the estimated parameters acquired during the message computation process. This combined approach effectively mitigates error propagation and premature convergence issues. The presented research offers a low-complexity decoding algorithm for LDPC codes, leveraging an optimized chaos bisection search method. The adoption of the LMMSE criterion overcomes data dependency and error propagation concerns during the estimation process. The modified chaos optimization technique, integrated with the bisection search, efficiently determines optimal values from perturbed observations, leading to improved convergence rates and data processing precision by reducing the observation dimension (search space). Simulation results validate the proposed approach, showcasing its ability to mitigate error propagation and premature convergence while maintaining coding gain accuracy. Experimental validation on an FPGA RF-SoC device (model XCZU27DR) demonstrates that the proposed method achieves a maximum throughput of 8.7 Gbps at a clock frequency of 386.72 MHz, with reduced hardware complexity. The experimental verification on an FPGA RF-SoC device highlights the algorithm's minimal hardware complexity, superior decoding throughput, and Bit Error Rate (BER) performance.

Validation of a New Method for Continuous Flare Combustion Efficiency Monitoring

A new method is described for calculating flare combustion efficiency (CE) and destruction and removal efficiency (DRE) using a numerical parametric model. The method combines key variables that affect flare performance including the flare vent gas net heating value (NHV), flare design, flow rate, exit velocity, and inert gas composition, alongside the environmental influence of crosswind speed. Each effect is characterized using a parametric model derived from experimental testing data and computational fluid dynamics (CFD). The inclusion of CFD allows the model to be extended into the high-wind conditions that cannot be adequately controlled for in empirical testing yet represent some of the most challenging conditions in which to maintain good combustion. This new parametric model method (PMM) is coupled with ultrasonic flowmeters from which the molecular weight and net heating value of the flare gas can be derived using the vent gas speed of sound measurement. In doing so, this method provides a reliable continuous flare combustion efficiency measure that can be deployed at scale with minimum hardware updates. The system was verified using an extractive sampling method with tests conducted on three full-scale industrial flares including non-assisted, single-arm pressure-assisted, and multi-arm pressure-assisted flare designs. A total of seventy valid test points were carried out with varying flow rate and flare gas heating value, covering a CE range from 46–100%. The uncertainty of the method was assessed using both traditional error propagation and Monte Carlo methodology. The results from the new method agree with the extractive method to within 0.8% in the ≥98% DRE region where flares are expected to operate to limit the impacts of flaring as a source of methane as a greenhouse gas. Uncertainty analysis revealed that the larger DRE discrepancy for DRE ≤ 98% correlates to the measurement uncertainties for both methods.

Performance and first measurements of the MAGIC stellar intensity interferometer

ABSTRACT In recent years, a new generation of optical intensity interferometers has emerged, leveraging the existing infrastructure of Imaging Atmospheric Cherenkov Telescopes (IACTs). The MAGIC telescopes host the MAGIC-SII system (Stellar Intensity Interferometer), implemented to investigate the feasibility and potential of this technique on IACTs. After the first successful measurements in 2019, the system was upgraded and now features a real-time, dead-time-free, 4-channel, GPU-based correlator. These hardware modifications allow seamless transitions between MAGIC’s standard very-high-energy gamma-ray observations and optical interferometry measurements within seconds. We establish the feasibility and potential of employing IACTs as competitive optical Intensity Interferometers with minimal hardware adjustments. The measurement of a total of 22 stellar diameters are reported, 9 corresponding to reference stars with previous comparable measurements, and 13 with no prior measurements. A prospective implementation involving telescopes from the forthcoming Cherenkov Telescope Array Observatory’s Northern hemisphere array, such as the first prototype of its Large-Sized Telescopes, LST-1, is technically viable. This integration would significantly enhance the sensitivity of the current system and broaden the UV-plane coverage. This advancement would enable the system to achieve competitive sensitivity with the current generation of long-baseline optical interferometers over blue wavelengths.

Leveraging the page buffer data cache for enhanced programmability in NAND flash memories with on‐chip microcontrollers

AbstractThis paper proposes a simple yet effective scheme for NAND Flash memories that employ on‐chip microcontroller units (MCUs) to manage internal array operations. Through minimal hardware overhead, the proposed scheme enables—without mask revision— executing new or updated array operations by leveraging the page buffer data cache instead of the hard‐wired on‐chip read‐only memory (ROM) for MCU instruction memory. While not applicable to ordinary user operations, this approach presents significant advantages across various stages of NAND flash memory development and implementation.

Building a Flexible and Resource-Light Monitoring Platform for a WLCG-Tier2

Software development projects at Edinburgh identified a desire to build and manage our own monitoring platform. This better allows us to support the developing and varied physics and computing interests of our Experimental Particle Physics group. This production platform enables oversight of international experimental data management, local software development projects and active monitoring of lab facilities within our research group. Larger sites such as CERN have access to many resources to support generalpurpose centralised monitoring solutions such as MONIT. At a WLCG Tier2 we only have access to a fraction of these resources and manpower. Recycling nodes from grid storage and borrowed capacity from our Tier2 Hypervisors has enabled us to build a reliable monitoring infrastructure. This also contributes back to our Tier2 management improving our operational and security monitoring. Shared experiences from larger sites gave us a head-start in building our own service monitoring (FluentD) and multi-protocol (AMQP/STOMP/UDP datagram) messaging frameworks atop both our Elasticsearch and OpenSearch clusters. This has been built with minimal hardware and software complexity, maximising maintainability, and reducing manpower costs. A secondary design goal has also been the ability to migrate and upgrade individual components with minimal service interruption. To achieve this, we made heavy use of different layers of containerisation (Podman/Docker), virtualization and NGINX web proxies. This presentation details our experiences in developing this platform from scratch with a focus on minimal resource use. This includes lessons learnt in deploying and comparing both an Elasticsearch and OpenSearch clusters, as well as designing various levels of automation and resiliency for our monitoring framework. This has culminated in us effectively indexing, parsing and storing >200GB of logging and monitoring data per day.

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.

OTK-based PUF CRP obfuscation for IoT device authentication

The use of a strong physical unclonable function (PUF) for device authentication in resource-limited settings is promising but susceptible to machine learning (ML) attacks. Several defenses have been suggested, but they often have drawbacks such as increased hardware requirements, compromised reliability, and limited effectiveness against sophisticated ML attacks. To overcome these challenges, a one-time key-based (OTK) obfuscation approach has been proposed aiming to bolster the security of robust PUFs when facing machine learning-based attacks. The main concept involves obtaining multiple stable responses from the PUF and selecting one as the initial key for challenge obfuscation. However, only the challenge input for the selected key is stored on the device side. The server stores all the stable challenge-response pairs and uses this selected key for the first authentication only. After every authentication, the input to the key is updated on both sides. For response obfuscation random number generated by the server is used. Our proposed method can effectively prevent ML attacks with minimal hardware requirements. Arbiter-PUF and Rely-PUF as case studies are analyzed. Experimental findings indicate that when applied to 64 × 64 Arbiter and Rely PUF, our method significantly reduces the effectiveness of various machine learning attacks, resulting in a prediction accuracy of approximately 50.6% and 50.96% respectively. This level of accuracy is comparable to random guessing. The 64-bit OTK-PUF boasts an impressively compact storage footprint, comprising merely 164 Look-Up Tables (LUTs), 276 flip-flops, and a 512-bit of read-only memory (ROM). The execution of the protocol on the Vitis platform takes a mere 0.02 s on the device side.

A Lightweight Image Encryption Scheme Using DNA Coding and Chaos

Protecting transmitted multimedia data such as images is a significant concern. This work proposes an encryption algorithm for greyscale images using a Pseudo-Random Number Generator (PRNG), DNA coding, and pixel sum. The proposed approach is implemented on a Genesys 2 FPGA using minimal hardware resources and can operate at a maximum frequency of 110.8 MHz. In addition, several performance evaluation tests are conducted for multiple images, including statistical analysis of the encrypted image, keyspace analysis, and differential attack analysis. The system is compared to recent works with respect to encryption quality and used hardware resources. The proposed scheme outperformed recent chaos-based image encryption schemes.

Cooling and anti-friction effects of vortex tube cryogenic minimum quantity lubrication in milling of 3D printed iron-nickel alloy

3D printed iron-nickel alloy is a promising engineering material with superior properties, which is widely applied in aerospace, nuclear and petrochemical industries. However, it is rather a difficult-to-cut material due to the insufficient cooling and lubrication, and the cost of tool usage is extremely high even with TiAlN coated or TiCN coated tools. Although some scholars have attempted to conduct the eco-friendly VT-cMQL (Vortex Tube-cryogenic Minimum Quantity Lubrication) system for machining iron-nickel alloy, this outdated VT-cMQL in Parallel mode still has huge shortcomings in terms of lubrication and anti-friction effects, energy consumption, and minimum hardware requirements. To solve this problem, this work proposed a new series VT-cMQL system in forms of Tandem I and Tandem II. The results show that the structure of new VT-cMQL system in Tandem I mode is simple, that only requires 1 air filter, 1 air compressor, 2 sections of pipe, and no T-joint is needed. The lowest cold flow temperature is −4.7 °C when the spray pressure, spraying distance, pipe length, and oil supply are 1.5 bar, 10 mm, 30 cm, and 45 ml/h, respectively. The cooling and anti-friction effect of VT-cMQL has little impact on milling tool's adhesion or oxidation, the main contribution is to further reduce abrasive wear. From the perspective of iron-nickel alloy industrial production, the new proposed VT-cMQL system can significantly reduce hardware configuration and improve the utilization of cryogenic compressed air.

Generalizable process monitoring for FFF 3D printing with machine vision

AbstractAdditive manufacturing has experienced a surge in popularity in both commercial and private sectors over the past decade due to the growing demand for affordable and highly customized products, which are often in direct opposition to the requirements of traditional subtractive manufacturing. Fused Filament Fabrication (FFF) has emerged as the most widely-used additive manufacturing technology, despite challenges associated with achieving contour accuracy. To address this issue, the authors have developed a novel camera-based process monitoring method that enables the detection of errors in the printing process through a layer-by-layer comparison of the actual contour and the target contour obtained via G-Code processing. This method is generalizable and can be applied to different printer models with minimal hardware adjustments using off-the-shelf components. The authors have demonstrated the effectiveness of this method in automatically detecting both coarse and small contour deviations in 3D-printed parts.

A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

Requirements for a processing-node quantum repeater on a real-world fiber grid

We numerically study the distribution of entanglement between the Dutch cities of Delft and Eindhoven realized with a processing-node quantum repeater and determine minimal hardware requirements for verifiable blind quantum computation using color centers and trapped ions. Our results are obtained considering restrictions imposed by a real-world fiber grid and using detailed hardware-specific models. By comparing our results to those we would obtain in idealized settings, we show that simplifications lead to a distorted picture of hardware demands, particularly on memory coherence and photon collection. We develop general machinery suitable for studying arbitrary processing-node repeater chains using NetSquid, a discrete-event simulator for quantum networks. This enables us to include time-dependent noise models and simulate repeater protocols with cut-offs, including the required classical control communication. We find minimal hardware requirements by solving an optimization problem using genetic algorithms on a high-performance-computing cluster. Our work provides guidance for further experimental progress, and showcases limitations of studying quantum-repeater requirements in idealized situations.

Neuromorphic Computing via Fission-based Broadband Frequency Generation.

The performance limitations of traditional computer architectures have led to the rise of brain-inspired hardware, with optical solutions gaining popularity due to the energy efficiency, high speed, and scalability of linear operations. However, the use of optics to emulate the synaptic activity of neurons has remained a challenge since the integration of nonlinear nodes is power-hungry and, thus, hard to scale. Neuromorphic wave computing offers a new paradigm for energy-efficient information processing, building upon transient and passively nonlinear interactions between optical modes in a waveguide. Here, an implementation of this concept is presented using broadband frequency conversion by coherent higher-order soliton fission in a single-mode fiber. It is shown that phase encoding on femtosecond pulses at the input, alongside frequency selection and weighting at the system output, makes transient spectro-temporal system states interpretable and allows for the energy-efficient emulation of various digital neural networks. The experiments in a compact, fully fiber-integrated setup substantiate an anticipated enhancement in computational performance with increasing system nonlinearity. The findings suggest that broadband frequency generation, accessible on-chip and in-fiber with off-the-shelf components, may challenge the traditional approach to node-based brain-inspired hardware design, ultimately leading to energy-efficient, scalable, and dependable computing with minimal optical hardware requirements.

A Single-Chip Single-Antenna Radar for Remote Vital Sign Monitoring

This article proposes an effective way to use self-injection locking (SIL) in a radar system to detect human chest cavity movement for vital signs monitoring with minimal hardware. The proposed approach expands the idea of using a phase-locked loop (PLL) system as a demodulator and a single antenna, making the system more compact. The system includes on-chip dc offset cancellation for system initialization. This work investigates and compares an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> -based voltage-controlled oscillator (LCVCO) and a ring voltage-controlled oscillator (RVCO) in terms of primary sensitivity for motion detection and phase noise. A study of injection-locking of both the LCVCO and RVCO is also established. The study shows that the RVCO is superior to the LCVCO in terms of sensitivity while the phase noise does not differ significantly as the frequencies of interest are very small, i.e., heart rate and respiration are bandwidth-limited to a few hertz. To verify the proposed idea, a design of both systems, an LCVCO-based PLL and an RVCO-based PLL, was implemented in 65 nm CMOS technology at 1.5 GHz. The simulation and measurement results confirm the idea proposed: the RVCO shows better performance across all metrics, e.g., higher sensitivity by 4 dB, lower power consumption by 30%, and reduced area (almost half) compared to the LCVCO.

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs

The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it offers over traditional 2D ICs. However, TSVs are susceptible to defects during their formation, die stacking, and operational lifespan, leading to reliability issues in 3D ICs. While existing approaches have focused on addressing assembly and stacking yield losses, the runtime failure caused by Electro-migration (EM) remains a significant challenge in commercializing TSV-based 3D ICs. Detecting and monitoring TSV defects require an expensive on-chip sensor network, making it crucial to implement a cost-effective TSV defect prevention and detection scheme. This paper introduces a runtime Built-in Self-prevention (BISP) scheme that significantly extends TSV lifetime. The proposed method employs a repair circuit to rectify post-manufacturing TSV defects, resulting in minimal hardware costs. Furthermore, the combined repair and prevention solution introduces a delay overhead of less than 0.5 ns, ensuring compliance with timing constraints.

Smartphone Imaging Flow Cytometry for High-Throughput Single-Cell Analysis.

We present a portable imaging flow cytometer comprising a smartphone, a small-footprint optical framework, and a PDMS-based microfluidic device. Flow cytometric analysis is performed in a sheathless manner via elasto-inertial focusing with a custom-written Android program, integrating a graphical user interface (GUI) that provides a high degree of user control over image acquisition. The proposed system offers two different operational modes. First, "post-processing" mode enables particle/cell sizing at throughputs of up to 67 000 particles/s. Alternatively, "real-time" mode allows for integrated cell/particle classification with machine learning at throughputs of 100 particles/s. To showcase the efficacy of our platform, polystyrene particles are accurately enumerated within heterogeneous populations using the post-processing mode. In real-time mode, an open-source machine learning algorithm is deployed within a custom-developed Android application to classify samples containing cells of similar size but with different morphologies. The flow cytometer can extract high-resolution bright-field images with a spatial resolution <700 nm using the developed machine learning-based algorithm, achieving classification accuracies of 97% and 93% for Jurkat and EL4 cells, respectively. Our results confirm that the smartphone imaging flow cytometer (sIFC) is capable of both enumerating single particles in flow and identifying morphological features with high resolution and minimal hardware.

A DV-Hop optimization localization algorithm based on topological structure similarity in three-dimensional wireless sensor networks

Localization technology performs an essential part in wireless sensor networks (WSNs). The Distance vector hop (DV-Hop) localization algorithm has been frequently used in the WSNs with its simplicity, feasibility and minimal hardware requirements. However, the low localization accuracy of the DV-Hop algorithm has limited its further application in WSNs. To overcome the accuracy problem of the DV-Hop algorithm, we propose an improved DV-Hop algorithm based on topological structure similarity, called TDSDV-Hop. Different from the traditional DV-Hop algorithm, the topological structure similarity is applied to correct the hop count, reducing the inaccuracy caused by the minimum hop count. The hop counts will be converted from discrete to precise continuous values by the topological structure similarity. In this paper, firstly, the topological structure similarity is defined, followed by the proof of the theory that the distance between two nodes is inversely proportional to the topological structure similarity. Secondly, a hop-correction equation that can correct the hop count between neighbor nodes is set up. Then the TDSDV-Hop algorithm incorporates hop-correction formula and simulates the optimal hop-correction parameters in order to acquire more accurate values of the hop count. And the coordinates of unknown nodes are calculated by the least square method. Finally, the levy adaptive improved bird swarm algorithm (LSABSA) is utilized to optimize coordinates of unknown nodes by constructing a new objective function. The simulation results show that the localization performance of the TDSDV-Hop algorithm is better than that of DV-Hop, GWODV-Hop, CRWDV-Hop and CVLR algorithm in terms of localization accuracy, localization time and communication cost.