Miller Capacitance Research Articles

Analog/RF characteristics of a 3D-Cyl underlap GAA-TFET based on a Ge source using fringing-field engineering for low-power applications

As an alternative to conventional tunnel field-effect transistor (TFET) devices for low-power applications, drain-underlap (DU) cylindrical (Cyl) gate-all-around (GAA) TFETs based on a Ge source using fringing-field effects can show suppressed subthreshold leakage current. In this work, such a fringing field is implemented using a hetero-spacer dielectric placed over the Ge source, resulting in enhanced direct-current (DC) and analog/radiofrequency (RF) characteristics such as $$I_{\mathrm{ON}}$$ , $$I_{\mathrm{OFF}}$$ , subthreshold swing (SS), $$C_{\mathrm{gs}}$$ , $$C_{\mathrm{gd}}$$ , and $$f_\mathrm{t}$$ . It is found that the ambipolar behavior and Miller capacitance $$C_{\mathrm{gd}}$$ are minimized in combination with a high band-to-band tunneling (BTBT) rate compared with devices based on a homo-spacer dielectric placed over a Si source. At the same time, the drain-underlap design increases the series resistance across the drain–channel junction overlapped by the fringing field, reducing $$I_{\mathrm{OFF}}$$ . Furthermore, the performance of the proposed device matches well with experimental data when including the effects of trap-assisted tunneling (TAT) for improved device reliability. Thus, the behavior of the RF figure of merit of the proposed device is different compared with conventional TFET designs.

Improving the Short-Circuit Reliability in IGBTs: How to Mitigate Oscillations

In this paper, the oscillation mechanism limiting the ruggedness of insulated gate bipolar transistors (IGBTs) is investigated through both circuit and device analysis. The work presented here is based on a time-domain approach for two different IGBT cell structures (i.e., trench-gate and planar), illustrating the two-dimensional effects during one oscillation cycle. It has been found that the gate capacitance varies according to the strength of the electric field near the emitter, which in turn leads to charge-storage effects associated with low carrier velocity. For the first time, it has been discovered that a parametric oscillation takes place during the short circuit in IGBTs, whose time-varying element is the Miller capacitance, which is involved in the amplification mechanism. This hypothesis has been validated through simulations and its mitigation is possible by increasing the electric field at the emitter of the IGBT with the purpose of counteracting the Kirk effect.

Role of Trench Bottom Shielding Region on Switching Characteristics of 4H-SiC Double-Trench Mosfets

The effect of a gate trench bottom p+ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

A nonlinear model to assess DC/AC performance reliability of submicron SiC MESFETs

A modified nonlinear model to predict direct-current (DC) and alternating-current (AC) characteristics of submicron SiC metal–semiconductor field-effect transistors (MESFETs) is presented. Such devices are normally operated under high-bias conditions, resulting in intense channel conditions and deviation from the usual device response. It has been demonstrated that, under relatively high drain bias, the Schottky barrier depletion is modified, causing the drain current to increase rapidly and thereby making the control of the Schottky barrier gate less effective. It has been observed that, when the ratio of the transconductance to the output conductance ( $$g_\mathrm{m}/g_\mathrm{d}$$ ) becomes less than unity, the device operational capabilities are drastically affected. Additionally, the small-signal intrinsic parameters of SiC MESFETs were assessed by evaluating the device Miller capacitances at various bias levels, revealing a significant increase in their magnitude at relatively high drain bias ( $$V_{\mathrm{ds}}\ge 40$$ V), which leads to deterioration of the high-frequency capabilities of the device, including the unity-gain frequency, $$f_\mathrm{T}$$ . Compared with the best reported model, the developed technique exhibited $$\sim 48\,\%$$ improved accuracy in predicting the I–V characteristics of submicron SiC MESFETs and $$\sim 63.5\,\%$$ improvement in evaluating the output conductance of the device. Thus, this technique can be employed to determine device reliability under intense operating conditions.

Study of the SOI LDMOS With Low Conduction Loss and Less Gate Charge

This brief focuses on the silicon-on-insulator (SOI) split gate (SG) superjunction (SJ) lateral double-diffused MOSFET (LDMOS), in which the p-column is not only utilized to compensate the fields produced by the opposite charges in the drift region, but also further acting as an SG. The accumulation layers of an electron are formed in the drift region during the on-state, providing the lower resistance paths for electric current, which leads to a decrease in the specific on-resistance ( ${R}_{\text {ON,sp}}$ ). Furthermore, because of the semiconductor-insulator-semiconductor (SIS) capacitor, not all of the positive charges in the n-drift region intend to induce the negative charges on the gate, since there is a Miller capacitance, and thus the gate charge ( ${Q}_{G}$ ) is reduced with the weakened Miller effect. The simulation results indicate that comparing with the previous SOI SJ-LDMOS, ${R}_{\text {ON,sp}}$ and ${Q}_{G}$ can be reduced by 35% and 17%, respectively, leading to a 46% improvement of figure of merit for the proposed structure.

Characterization and Performance Evaluation of the Superjunction RB-IGBT in Matrix Converter

In this paper, we investigate the performance of the three-phase ac–ac matrix converter (MC) utilizing the novel superjunction (SJ) reverse-blocking (RB)-insulated gate bipolar transistor (IGBT) as switch elements for the first time. The SJ RB-IGBT offers bidirectional blocking capability >1200 V by introducing a shorted-collector trench and n2-layer. The SJ RB-IGBT exhibits bipolar conducting mode in the on-state and the unipolar mode during turn-off. Therefore, both a low on-state voltage ( V on) and a low turnoff energy loss ( E off) can be obtained. The SJ RB-IGBT delivers the E off 80% lower than state-of-the-art RB-IGBTs without penalty in the V on. These merits make the SJ RB-IGBT an attractive candidate for the MC. To address the short circuit arising in commutation of the MC, the split gate is adopted for a low Miller capacitance. The power loss, efficiency, and loss distribution of the three-phase MC with the SJ RB-IGBT and other RB-IGBTs are compared by simulation and calculation. Compared with the MC using conventional nonpunch-through RB-IGBT, the MC with SJ RB-IGBT achieves 85%, 87%, and 56% reductions in the turnoff, reverse recovery, and conduction losses, respectively, yielding 56% reduction in the total loss. The low-power loss and superior dynamic performance of the SJ RB-IGBT enables the MC to operate at higher frequency and higher power density.

Symptom reliability: S‐parameters evaluation of power laterally diffused‐metal–oxide–semiconductor field‐effect transistor after pulsed‐RF life tests for a radar application

This paper treats the s -parameter performance degradation by hot electron induced for N-MOSFET devices used in radar applications. This study is relevant for devices operating in the RF frequency regime. The power LD-MOSFET device (0.8 µm channel length, Gate oxide thickness 0.065 µm and 2.2 GHz) are designed and fabricated. Subsequently, life tests in pulsed RF cause, after ageing, the electrical behaviour and its relation with charge trapping at the interface are presented and discussed. Unlike all other current methods, a complete evaluation of S parameters is carried out to obtain key information concerning the defects location. The s -parameter performance degradation can be explained by the transconductance and the miller capacitance move, and by the leakage current augmentation IG, which is shown by hot-carrier event from the Si/SiO 2 interface state generation and/or in a build up of negative charge. Also, the degradation can be predicted by the experimental correlation of RF and dc performance shifts, favour by the measurement of dc performance or initial leakage current. The analysis accompanied proves that the s -parameters shift by hot electron induced and should be taken into consideration in the design. Through physical processes of ATLAS-SILVACO simulations these degradation phenomena are located and confirmed

Three stages CMOS operational amplifier frequency compensation using single Miller capacitor and differential feedback path

This study describes a new and simple frequency compensation for three stages amplifiers based on revered nested Miller compensation (RNMC) structure. Using only one and small compensation capacitor reduced circuit complexity and die area while shows better performance compared to RNMC. Also the proposed method is unconditional stable due to cancellation of second dominant pole by a zero. Ample simulations are performed using HSPICE and TSMC 0.18 µm CMOS technology to verify robustness of presented circuit. Simulation results show 114 dB, 6.66 MHz and 360 µW as DC gain, GBW and power consumption respectively.

A Two Stage Op-Amp Phase Margin Symbolic Expression

A phase margin symbolic expression of a two stage Miller compensated operational amplifier is computed in this paper. Using this expression, an analysis to evaluate the influence of the Miller and load capacitance on phase margin is performed. This way, a designer can rapidly choose the optimal set of values to fulfil an imposed phase margin. The phase margin expression is based on poles/zeros symbolic expressions obtained using a symbolic LR algorithm able to compute both the numerical values and the approximate symbolic expressions of poles and zeros of a circuit. The numerical values obtained with this algorithm are compared with those computed by SPECTRE. The example is a two stage Miller compensated operational amplifier designed in a 180nm CMOS technology.

Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap

A compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dg</sub> ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developedwhich enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit.

Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.

A systematic investigation of the integrated effects of gate underlapping, dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of $$\mathrm{SiO}_{2}$$ as the gate dielectric. Therefore, a hetero gate dielectric $$\mathrm{SiO}_{2}$$ on the drain side and $$\mathrm{HfO}_{2}$$ on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.

An Accurate Subcircuit Model of SiC Half-Bridge Module for Switching-Loss Optimization

The increasing demand for high power density requires the power converter to operate in high switching frequency. Silicon carbide (SiC) power module is regarded as one of the most promising candidates for high-frequency applications due to the superior switching speed and low switching loss. With the increase of switching frequency, the switching loss will be the limiting factor of efficiency. Hence, it should be minimized during each switching transition. The optimization of switching loss is normally achieved by the repetitive double pulse test experiments. It is time-consuming to find an optimum gate resistance to achieve the tradeoff between switching loss and electromagnetic interface. In this paper, an accurate subcircuit model for SiC power module is proposed to assist optimization of switching loss in converter design. By considering the device physics and structure, an accurate Miller capacitance model is obtained. Moreover, a parameter extraction procedure is presented, which is based on the datasheet. Good agreements are achieved between the PSpice simulation and experiment.

Experimental Investigation of ${C}$ – ${V}$ Characteristics of Si Tunnel FETs

This letter presents an experimental capacitance–voltage ${C}$ – ${V}$ analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance ${C}_{\textsf {gs}}$ to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance ${C}_{\textsf {gd}}$ at higher ${V}_{\textsf {ds}}$ and ${V}_{g}$ . Comparable values of ${C}_{\textsf {gs}}$ and ${C}_{\textsf {gd}}$ would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations.

On the Source of Oscillatory Behaviour during Switching of Power Enhancement Mode GaN HEMTs

With Gallium Nitride (GaN) device technology for power electronics applications being ramped up for volume production, an increasing amount of research is now focused on the performance of GaN power devices in circuits. In this study, an enhancement mode GaN high electron mobility transistor (HEMT) is switched in a clamped inductive switching configuration with the aim of investigating the source of oscillatory effects observed. These arise as a result of the increased switching speed capability of GaN devices compared to their silicon counterparts. The study identifies the two major mechanisms (Miller capacitance charge and parasitic common source inductance) that can lead to ringing behaviour during turn-off and considers the effect of temperature on the latter. Furthermore, the experimental results are backed by SPICE modelling to evaluate the contribution of different circuit components to oscillations. The study concludes with good design techniques that can suppress the effects discussed.

On the Source of Oscillatory Behaviour during Switching of Power Enhancement Mode GaN HEMTs

With Gallium Nitride (GaN) device technology for power electronics applications being ramped up for volume production, an increasing amount of research is now focused on the performance of GaN power devices in circuits. In this study, an enhancement mode GaN high electron mobility transistor (HEMT) is switched in a clamped inductive switching configuration with the aim of investigating the source of oscillatory effects observed. These arise as a result of the increased switching speed capability of GaN devices compared to their silicon counterparts. The study identifies the two major mechanisms (Miller capacitance charge and parasitic common source inductance) that can lead to ringing behaviour during turn-off and considers the effect of temperature on the latter. Furthermore, the experimental results are backed by SPICE modelling to evaluate the contribution of different circuit components to oscillations. The study concludes with good design techniques that can suppress the effects discussed.

Reduced Miller Capacitance in U-Shaped Channel Tunneling FET by Introducing Heterogeneous Gate Dielectric

In this letter, a novel U-shaped channel tunneling FET (UTFET) with heterogeneous gate dielectric (HG-UTFET) is designed to reduce the Miller capacitance ( $\text{C}_{\mathrm {\mathbf {M}}}$ ) and to improve the performance of TFET digital circuits. Because the HG-UTFET and UTFET have the same gate dielectric near the source region, these two devices nearly have the same on-state current. But due to the smaller gate-to-drain capacitance ( $\text{C}_{\textit {gd}}$ ) caused by the low- ${k}$ gate dielectric near the drain region, the HG-UTFET has smaller $\text{C}_{\mathrm {M}}$ compared with UTFET, which will enhance the switching performance of digital circuits. The simulation results reveal that the overshoot/undershoot and rising/falling delay of the output signal in the HG-UTFET inverter are reduced a lot compared with the UTFET inverter. Results show that the $\text{C}_{\mathrm {M}}$ and falling delay of the HG-UTFET inverter are ~45.6% and ~30.7% less than that of the UTFET inverter, respectively. Therefore, by the application of HG-UTFET, the switching performance of inverter can be enhanced a lot.

High-speed Cherry Hooper flash analog-to-digital converter

PurposeThe 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies.Design/methodology/approachThe CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The C-H differential amplifier is modified to accommodate the low breakdown voltages of the technology node and implemented as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm SiGe BiCMOS 8HP technology node. Measurements were carried out on test printed circuit boards and compared with simulation results.FindingsThe use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture, for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity and differential non-linearity was 0.33 LSB. The prototype ADC had a figure of merit of 42 pJ/sample.Originality/valueThe prototype ADC results showed that the group delay for the C-H comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation, the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC C-H ADC is capable of achieving an ENOB close to 1.18, for frequencies up to 2 GHz, with 180 mW total power consumption.

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

ANALYSIS OF HETEROJUNCTION TUNNELING ARCHITECTURES FOR ULTRA LOW POWER APPLICATIONS

Ponte Academic JournalOct 2017, Volume 73, Issue 10 ANALYSIS OF HETEROJUNCTION TUNNELING ARCHITECTURES FOR ULTRA LOW POWER APPLICATIONSAuthor(s): B V V SATYANARAYANA ,M.Durga PrakashJ. Ponte - Oct 2017 - Volume 73 - Issue 10 doi: 10.21506/j.ponte.2017.10.9 Abstract:Tremendous revolutionary changes lead the electronic industry from the past eight decades. Nowadays, portable electronic systems play a major role in the human life. These systems consist of adders, multiplexers, registers, memories etc. But memories are more power consuming components in embedded applications. In general, embedded systems are equipped with large battery sources in order to avoid frequent charging of batteries. The capacity of the battery depends on the power consumption of the system. Higher the power consumption can higher the battery capacity and hence the size which is unacceptable for portable embedded systems. So we need effective low power VLSI techniques for better performance of integrated systems. Many authors propose low power techniques for design and implementation of systems; the most effective energy saving method is low voltage operation. Heterojunction tunneling structures operated in the low subthreshold region of the transistor. This work presents the analysis of different types of heterojunction tunneling architectures for low power as well as ultra low power applications. A comparative analysis of heterojunction architectures can be done with reference to ION / IOFF ratio, leakage current, subthreshold swing (SS) and materials used for manufacturing and it needs a trade-off among these parameters. So, we proposed an architecture that addresses High ION / IOFF ratio, steeper subthreshold swing and improved Miller capacitance with less leakage current. These structures give a great compromise between power consumption and performance (speed and power trade-off) and hence improving the performance of heterojunction architectures. Download full text:Check if you have access through your login credentials or your institution Username Password