Experimental Investigation of ${C}$ – ${V}$ Characteristics of Si Tunnel FETs

Abstract

This letter presents an experimental capacitance–voltage ${C}$ – ${V}$ analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance ${C}_{\textsf {gs}}$ to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance ${C}_{\textsf {gd}}$ at higher ${V}_{\textsf {ds}}$ and ${V}_{g}$ . Comparable values of ${C}_{\textsf {gs}}$ and ${C}_{\textsf {gd}}$ would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations.