Miller Capacitance Research Articles

A controllable resistor and its applications in pole-zero tracking frequency compensation methods for LDOs

This paper presents a controllable resistor, which is formed by a MOS-resistor working in the deep triangle region and an auxiliary circuit. The auxiliary circuit can generate the gate-source voltage which is proportional to the output current of an low dropout regulator for the MOS-resistor. Thus, the equivalent output resistance of the MOS-resistor is inversely proportional to the output current, which is a suitable feature for pole-zero tracking frequency compensation methods. By switching the type of the MOS-resistor and current direction through the auxiliary circuit, the controllable resistor can be suitable for different applications. Three pole-zero tracking frequency compensation methods based on a single Miller capacitor with nulling resistor, unit-gain compensation cell and pseudo-ESR (equivalent serial resistor of load capacitor) power stage have been realized by this controllable resistor. Their advantages and limitations are discussed and verified by simulation results.

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

AbstractReduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

A Fully Integrated SiGe Optical Receiver Using Differential Active Miller Capacitor for 4.25 Gbit/s Fiber Channel Application

This paper provides a SiGe optical receiver using new high performance differential active Miller capacitor (DAMC) circuits to replace off-chip capacitors. The fully integrated design can avoid off-chip noise interference. The 4.25 Gbit/s optical receiver was realized in a commercial 0.35 µm SiGe BiCMOS process. The measured results of the receiver demonstrate a differential output swing of 530 mV with 50 Ω output loads, a crossing percentage of 51.6%, a peak-to-peak jitter (jitterp–p) of 23.9 ps, and an input sensitivity of -13.8 dBm, respectively, at a bit error rate (BER) of 10-12 with a 231-1 pseudo random binary sequences (PRBS) test pattern. The total circuit dissipates 105.6 mW under a 3.3 V supply, and the chip size is 945 ×980 µm2.

Design of a 1-V 1-MS/s Track&Hold circuit based on the switched opamp approach

A very low voltage solution for the realization of the hold capacitor in a Track&Hold circuit based on an open-loop architecture is introduced. The circuit is a modification based on the switched opamp approach of the Track&Hold circuit using Miller Capacitance. Simulations show that the circuit is able to operate at 1V 1MS/s with a Total Harmonic Distortion of −64 dB @ 100 kHz and a very low power consumption of 80 µW.

Fully-differential self-biased bio-potential amplifier

A highly versatile and programmable bio-potential recording amplifier is presented. The amplifier achieves low-power operation with minimal size by using a fully-differential self-biased operational amplifier and the Miller capacitance technique. The experimental results of recording various biological signals are provided.

Fast-Transient DC–DC Converter With On-Chip Compensated Error Amplifier

A fast-transient dc-dc converter with on-chip compensated error amplifier is presented in this paper. The error amplifier uses three transistors and one voltage follower to implement the on-chip current-mode Miller capacitor. Not only on-chip compensated error amplifier is implemented without off-chip components and I/O pins, but also fast-transient response is achieved. Moreover, we accurately decrease the transient response time without suffering from the oscillation issue. Implemented in a 0.35-mum CMOS process, experimental results demonstrate the stability of converters with a little area overhead about 5% larger than that of conventional design. In case of load variations, there is about four times reduction on the dropout voltage compared to that of conventional design. Furthermore, transient speed by our proposed technique is about five times faster than that of conventional control, while the total quiescent current is only increased about 3%.

Single Miller capacitor frequency compensation with nulling resistor for three‐stage amplifiers

AbstractA frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley & Sons, Ltd.

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I DS and different extremes temperatures Δ T values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO 2 interface.

Notice of Violation of IEEE Publication Principles A 54 dBOmega + 42 dB 10 Gb/s SiGe transimpedance-limiting amplifier using bootstrap photodiode capacitance neutralization and vertical threshold adjustment

A high-gain 10 Gb/s transimpedance-limiting amplifier (TIA-LA) capable of directly driving a SERDES IC was realized in a 60 GHz fT 0.2 mum SiGe BiCMOS SOI process. The shunt-feedback common-emitter input stage uses a bootstrap technique to neutralize the photodiode parasitic capacitance. Cascode configurations and cross-coupled Miller capacitance cancellation were used to minimize the input capacitance of the signal path stages. This reduces the number of inter-stage isolation emitter- followers, allowing low-voltage operation. A signal-amplitude-dependent adjustable threshold was implemented in the back-end limiting stages by using inverse hyperbolic tangent circuits. Integrating the high-gain TIA-LA signal path on the same die was made possible by using an SOI process in conjunction with die thinning to reduce substrate coupling and minimizing the output-to- input bondwire magnetic coupling through a careful pin location selection. The main limiting-TIA IC specifications include: 96 dBOmega total gain given by 54 dBOmega TIA gain and 42 dB LA voltage gain, 12 muA input sensitivity, < 8 pA/ radicHz input equivalent noise, 0.3 W power consumption from a 3.3 V supply and 1.8 times 1.8 mm2 die area.

Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N −channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO 2/Si barrier.

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO2 barrier.

1200-V Low-Loss IGBT Module With Low Noise Characteristics and High ${d}I_{C}/{d}t$ Controllability

This paper presents the enhanced characteristics of a newly developed low-loss and low-noise 1200-V insulated gate bipolar transistor (IGBT) module. In order to realize low-noise emission, it is necessary not only to improve the reverse recovery characteristics of the free wheeling diode (FWD) but also to reduce the low-current turn-on dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> /dt of the IGBT. The new IGBTs with high turn-on dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C </sub> /dt controllability and low turn-on power dissipation have been successfully developed by the reduction of Miller capacitance resulting from an optimization of the surface. The 1200-V 450-A IGBT module utilizing the new IGBT and optimized FWD chips has been able to realize 30% reduction of the switching power dissipation when compared to the conventional IGBT module under the operating condition to set the same noise emission level

Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter

This paper proposes a Miller capacitor which has a wide input signal range. By discharging the charge of the capacitor connected between the input and output terminals of an amplifier before the output voltage of the amplifier exceeds its maximum range, the amplifier always operates in the active region and the Miller operation can be guaranteed. Thus a large value capacitor with a wide dynamic operation range can be realized using a small value capacitor. The Miller capacitor proposed in this paper is applied to a loop filter of phase locked loop (PLL) circuit that requires a large value capacitor to realize a low cutoff frequency. SPICE simulation of the PLL circuit using the Miller capacitor confirms the operation of the Miller capacitor and shows good performances that are similar to those obtained using a passive capacitor of a large value.

SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the width of the PMOS and NMOS transistors, which determines the relationship between the currents passed along the pull-up and pull-down paths. The variation of the pull-up to pull-down ratio for different circuit parameters is discussed in this paper under the constraint of equal rise and fall delay times. It is shown that the short-circuit current and the Miller capacitance affect the ideal linear relationship between the CMOS inverter delay times and the load capacitance, requiring the pull-up to pull-down ratio to be adjusted as circuit parameters are varied. These effects are more pronounced in deep submicrometer technologies with significant parasitic MOSFET capacitances and threshold voltage variations. Based on analytic and experimental observations, circuit design guidelines are proposed to minimize the Miller effect.

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.

CMOS low dropout linear regulator with single Miller capacitor

A 2–5V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 µm CMOS process and the active chip area is 485×586 µm. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.

&amp;lt;tex&amp;gt;$DV/DT$&amp;lt;/tex&amp;gt;Related Spurious Gate Turn-On of Bidirectional Switches in a High-Frequency Cycloconverter

We identified a failure mode in a two stage dc/ac converter, comprising a high-frequency dc/ac inverter followed by an ac/ac cycloconverter, both operating at the same switching frequency. The failure-mode is a short-circuit condition, which is a combined effect of the reverse recovery of the MOSFET body diode and simultaneous spurious turn-on of the bidirectional switches of the cycloconverter, owing to a significantly high dv/dt (>2/spl times/10/sup 8/V/ns). A high dv/dt causes appreciable current to flow through the gate-to-drain (Miller) capacitance, thereby producing a significant amount of voltage drop across the external gate resistance. Consequently, the gate-to-source voltage of the power MOSFET may exceed the threshold voltage of the device, which turns the device on. We explain the mechanism for the dv/dt-related gate turn-on and present experimental results to validate the explanation. We also demonstrate, how a two-fold increase in the value of external gate resistance of the inverter switches (to reduce the dv/dt applied to the cycloconverter) reduces the periodicity of the short-circuit condition.

Design procedure for two-stage CMOS operational amplifiers employing current buffer

The design procedure of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a pair of nondominant complex conjugate poles and a finite zero, the proposed procedure is based upon the design strategy that results in the opamp with only one dominant pole. Design example of the proposed procedure is given.

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.