Miller Capacitance Research Articles

Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators

This paper presents a general methodology for compensating LDO regulators which exploits a current amplifier to effectively multiply the Miller capacitor. After a general theoretical analysis that takes into account both the external and internal loop stability, it is examined the feasibility of applying this kind of compensation in different LDO applications, showing the role of the design parameters and proposing a specific design procedure for each practical cases which differ in terms of load capacitance and the adoption of a decoupling voltage buffer. Simulations and experimental results which validate the methodology are also included.

Distortion Modeling of Feedback Two-Stage Amplifier Compensated With Miller Capacitor and Nulling Resistor

Accurate distortion modeling of feedback amplifier with Miller compensation is the main subject of this paper. Inspired by traditional Rosenstark method, a nonlinear signal-flow-based method has been developed. Based on the proposed method, the nonlinear coefficients of each gain stage can be evaluated exactly and the rules of cascading, feedback can be found conveniently. As a result, the second- and third-order harmonic distortion factors are obtained in a simple manner. The application range includes all kinds of Miller compensation strategies with or without feedforward compensation path. The distortion modeling of a two-stage opamp compensated with Miller capacitor and nulling resistor is used to show versatility of the proposed method. In addition, simplified distortion factor expressions, approximate characteristic frequencies of the distortion factors and the value of external configuration resistors for canceling the second-order harmonic components at DC are also derived and can be used to accelerate distortion evaluation of opamp designs. Accuracy of the method was verified by comparing the results between theoretical analysis and transistor level simulation.

SSTA Scheme for Multiple Input Switching Case Based on Stochastic Collocation Method

In this paper, a complete SSTA scheme is proposed to calculate the output waveform of a logic cell on any random selected point in the process variational space, or the mean value and variance of the output signal with very high accuracy and acceptable CPU cost. At first, Miller capacitances between the input nodes and internal nodes of a logic cell are introduced to construct the improved MCSM model so as to improve the modeling accuracy. Secondly, the stochastic collocation method jointed with the Modified Nested Sparse Grid technique is adopted for SSTA procedure to avoid the exponential increase of the collocation points number caused by tensor product. Thirdly, a Nominal waveform based Fast Simulation Method is developed to speedup the simulation on each collocation point. At last, Automatic Waveform Construction Technique is developed to construct the output waveform with the approximation points as little as possible to decrease the computational cost while guaranteeing high accuracy. Numerical results are also given to demonstrate the efficiency of the proposed algorithm.

Non-Overlapping clock delay generation using Miller capacitor

Non-Overlapping clock delay generation using Miller capacitor

A Wideband Variable Gain Amplifier using 0.13m CMOS Technology

A wideband variable gain amplifier (VGA) design is introduced with two different schemes. It is based on a fully differential amplifier with resistive loads and a Negative Miller Capacitance technique is used to increase the bandwidth of the amplifier. The amplifier consists of three stages and the gain is varied using the second and third stages, where they are degenerated by a voltage controlled variable resistance. The design is ready to be implemented with MOSFETs using UMC 0.13mm technology. The supply voltage is 1.2V, and achieved gain is up to 35 dB with a minimum bandwidth of 1 GHz. Two design schemes are discussed, describing the tradeoff between the dynamic range of the variable gain and the bandwidth.

S-parameter performance degradation in power RF N-LDMOS devices due to hot carrier effects

This paper reports comparative study of technology reliability after accelerated ageing tests under various conditions (electrical and/or thermal stress) and RF life-tests reliability with pulsed bench for radar applications in S-band. It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters.The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS–SILVACO simulations.S-parameters degradation of hot-carrier stressed n-MOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. From our experimental results, hot electron induced RF performance degradation should be taken into consideration in the design of the power RF MOS devices.

A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

A 2 Gb/s optical receiver with monolithically integrated MSM photodetector in standard CMOS process

A monolithically standard complementary-metal-oxide-semiconductor (CMOS) optical receiver with a metal-semiconductor-metal (MSM) photodetector is presented in this paper. An active-feedback transimpedance amplifier (TIA) with negative Miller capacitance is used to increase the bandwidth of the receiver. The MSM photodetector with high responsivity provides higher sensitivity for the optical receiver. The optical receiver implemented in chartered 0.35 μm process achieves a 1.7 GHz bandwidth due to the low capacitance of the MSM photodetector. 2 Gb/s optical data are successfully transmitted with a bit-error rate of 10−9 at an optical power of −15 dBm. The power consumption of the receiver is 94 mW under a single 3.3 V supply.

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In0.6Ga0.4As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption.

Design of a high frequency low voltage CMOS operational amplifier

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

HHNEC 0.18um BCD Technology for High Density Power Integration

A new 0.18um Bipolar CMOS DMOS (BCD) integrated platform is presented. This technology provides both N type and P type power LDMOS with capability of voltage up to 40V applications; these power LDMOS devices have competitive specific on-resistance; the parasitical miller capacitance and SOA of power LDMOS devices are optimized by careful device and layout design; it also provides HVCMOS with voltage up to 40V analog application; the bipolar devices in this technology are also optimized for power switching as standard bipolar process offers. The 1.8V/5.0V CMOS devices are performance compatible with industry main stream 1.8V/5.0V CMOS technology. This platform is modularized with various options; it can be separated into 1.8V/5.0V mixed 40V HVCMOS process, 5.0V Vgs 40V Vds 0.18um backend BCD process and 1.8V/5.0V Vgs 40V Vds 0.18um BCD process, which customers can easily choose for their product needs without any process tuning.

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.

Electrical Characterization of 10-nm π-Shaped S/D MOSFETs

In this paper, we numerically explore electrical characteristics of a simple device called the π-shaped source/drain (π-S/D) MOS transistor. Some techniques such as Si/SiGe epitaxial growth and selective SiGe etch process are implemented for the fabrication of quasi-SOI devices with an S/D tie. More importantly, a new method presented here for fabricating π-S/D MOSFETs does not require any additional mask step due to self-alignment process being exploited. The isolation technique is carried out only after S/D annealing, resulting in only four extra process steps introduced in this new quasi-SOI technology. According to numerical simulations, the new π-S/D structure has better control on the short-channel and thermal effects compared with the conventional (conv.) π-S/D structure. Despite Miller capacitance sacrifice behaviour owing to the absence of the conv. isolation approach before gate definition, which causes an increase in the body area under the gate, NMOSFET intrinsic delay τ and cutoff frequency f T are within acceptable limits for this new structure.

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization

This paper presents an optical receiver with a monolithically integrated photodetector in 0.18-μm CMOS technology using a combination of spatially modulated light (SML) detection and an analog equalizer. A transimpedance amplifier employing negative Miller capacitance is introduced to increase its bandwidth without causing gain peaking. To provide sufficient reverse-bias voltage to the photodetector's p-n junction, the transimpedance amplifier is operated with a 3.3-V supply, while the rest of the circuit blocks is powered with a 1.8-V supply. The on-chip SML detector achieves a net responsivity of 0.052 A/W. Occupying a core area of 0.72 mm2, the fully integrated optical receiver achieves 4.25 and 5 Gbits/s with power consumption values of 144 and 183 mW, respectively.

A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors

This paper presents a synthesis of hot-electron effects on power RF LDMOS performances, after accelerated ageing tests with electrical and/or thermal stress. Which can modify and degrade transistor physical and electrical behaviour. The effects of reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters are pointed out. The RF performance degradation is explained primarily by the transconductance and miller capacitance shifts. To reach a better understanding of the physical mechanisms of parameter’s shift after ageing tests, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge.

Fully-integrated transimpedance amplifier for photoplethysmographic signal processing with two-stage Miller capacitance multiplier

A two-stage Miller capacitance multiplier for compensation is proposed to implement an ultra-low frequency fully-integrated transimpedance amplifier (TIA). With the proposed multiplier, the TIA achieves a passband gain of 89 dBΩ, a DC current rejection ranging from 0.5 to 85 µA, and a −3 dB highpass cutoff frequency of 0.5 to 9.5 Hz. This corresponds to an improvement of six times in DC current rejection range compared with previous techniques.

On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

We compare the transient response of double-gate thin-body-silicon interband tunnel field-effect transistor (TFET) with its metal-oxide-semiconductor field-effect transistor counterpart. Due to the presence of source side tunneling barrier, the silicon TFETs exhibit enhanced Miller capacitance, resulting in large voltage overshoot/undershoot in its large-signal switching characteristics. This adversely impacts the performance of Si TFETs for digital logic applications. It is shown that TFETs based on lower bandgap and lower density of states materials like indium arsenide show significant improvement in switching behavior due to its lower capacitance and higher ON current at reduced voltages.