Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors

Abstract

This paper presents a synthesis of hot-electron effects on power RF LDMOS performances, after accelerated ageing tests with electrical and/or thermal stress. Which can modify and degrade transistor physical and electrical behaviour. The effects of reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters are pointed out. The RF performance degradation is explained primarily by the transconductance and miller capacitance shifts. To reach a better understanding of the physical mechanisms of parameter’s shift after ageing tests, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge.