Middle Of Line Research Articles

Effect of Stray Capacitance in a Distribution Network on the Accuracy of Fault Location Based on Electromagnetic Time Reversal Method

The existing electromagnetic time reversal (EMTR) method for determining the location of faults in a distribution system does not consider stray capacitors in the system, leading to inaccurate fault location results. In this article, the influence of stray capacitors at the end and middle of the line on the EMTR method without considering the capacitance in the backward-time process was analyzed, the current signal energy of the fault location was derived, and the fault location was determined. A reduced-scale experimental platform of the EMTR method was built, and the influence of stray capacitors at observation points and middle of lines on the fault location results was verified. Finally, a fault location platform for a 33-node distribution network was built in power systems computer aided design (PSCAD) to explore the impact of stray capacitance on the fault location accuracy. The results showed that the error increases with the increase of the stray capacitance. This article found that considering the stray capacitance in the backward-time process can help determine the fault location more accurately. Besides, the signal observation point setting at low time constant area can also improve the accuracy when stray capacitance cannot be determined.

Suppression of Dissolution Rate via Coordination Complex in Tungsten Chemical Mechanical Planarization

Topography of tungsten should be assured at a minimum through chemical mechanical planarization (CMP) in the metal gate structures (e.g., buried gates, replacement metal gates) and via contact in the middle of line (MOL) process for sub−7 nm semiconductor applications. However, excessive tungsten dissolution during the CMP process that results from high oxidizer concentrations and acidic atmospheres results in poor tungsten topography. In this study, we report a novel strategy to improve the tungsten topography by suppressing tungsten dissolution via coordination complex formations between picolinic acid and tungsten oxide. With 1.5 wt% picolinic acid for the inhibitor, the dissolution rate of tungsten was dramatically attenuated, and improved topography with a Ra value of 7.8 nm were demonstrated while validating CMP removal rate.

Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit

With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back-end-of-line (BEOL) on the circuit performance. We constructed a process design kit (PDK) for path-finding to analyze the circuit layout in a 3nm technology node based on gate-all-around FET (GAA-FET). It consists of the spice model library that satisfies the 3nm power performance area (PPA) target, and the layout versus schematic (LVS), parasitic extraction (PEX) model that checks whether the layout and schematic match, extracts the RC values in the FEOL MOL and BEOL areas. Subsequently, the effect of the interconnection on complex logic circuits (RO, full adder) was confirmed using PDK. As a result of quantifying the effects of FEOL, MOL, and BEOL on the circuit, circuit degradation due to the RC of MOL and BEOL accounts for more than 60%. Furthermore, we introduced the air spacer process as a way to improve the circuit performance by reducing the CMOL owing to the reduction in the dielectric constant of the spacer. When an air spacer is introduced, based on 9-stages FO1 INV RO with k = 7 at V_DD = 0.7V, under iso-speed condition, the active power decreases by 30%, 35% when k is 3.3, 1.65, respectively. Under iso-power condition, frequency increases by 9%, 11% when k is 3.3, 1.65, respectively. And based on full adder with k = 7 at V_DD = 0.7V, Under iso-speed conditions, the active power decreases by 47%, 58% when k is 3.3, 1.65, respectively. Under iso-power conditions, the delay decreases by 14%, 20% when k is 3.3, 1.65, respectively. PDP decreases by 22%, 32% when k is 3.3, 1.65, respectively. EDP decreases by 31%, 44% when k is 3.3, 1.65, respectively. In conclusion, in this work, we provide a guide for determining the BEOL load and developing an improved wiring process.

Materials to Systems Co-Optimization Platform for Rapid Technology Development Targeting Future Generation CMOS Nodes

Design technology co-optimization (DTCO) has been a workhorse in optimizing logic technology innovations for a few generations now. With increased complexity associated with each new node and the growing number of technological innovations, it is time to expand the conventional DTCO flows. In this article, we present a novel materials to systems co-optimization (MSCO) platform, expanding the boundaries of traditional DTCO to encompass materials modeling to all the way to system design. To demonstrate the application of our MSCO platform, we discuss various front-end-of-line (FEOL) and middle-of-line (MOL)/back-end-of-line (BEOL) technologies and show their impact on device and circuit performance.

Intelligent MOL(Middle-Of-Line) Design Methodology for 3D FinFET Manufacturability

This research is an outstanding first study on the intelligent design methodology of the core MOL scheme. It can maximize the manufacturability of 3D FinFET technology that is mainly used for foundry AP products ranging from 10nm to 5nm.In order to realize various MOL structures, 3D virtual process simulation considering plasma and surface reaction was implemented, and based on this, the generation of gate to contact short, a chronic defect in FinFET MOL scheme, could be detected without decap. Futhermore, for the feature selection, the process factor sensitivity analysis was performed with the Monte carlo algorithm, which is one of the representative reinforcement learning techniques, and it was found that the key factors of defect were gate to contact misalign and contact etch angle. In the Gate-to-Contact 3D minimum distance probability distribution function generated by millions of samplings based on this intelligent algorithm, the failure criteria can be obtained by mapping with the number of fail bits detected in the wafer.As the device's scaling limit was reached, SCE-driven FEOL(Front-End-Of-Line) characteristics as well as the MOL parasitics' portion became very huge in the 10 nm or less FinFET technology, but all studies have been limited to the effects of device performance via RC(Resistance-Capacitance) analysis.On the other hand, our methodology provides a 3D minimum distance 5.7nm specification for a defect-free MOL structure for the first time, and provides conditions to meet Gate to CNT short zero at the current process capability level when improving M/A 4.5nm and etch ang 1.5o. In silicon, the same result was obtained as predicted. Figure 1

Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.

Enhanced Reliability of 7-nm Process Technology Featuring EUV

In this article, we report the reliability characterization of 7-nm technology, in which the highly scaled sixth generation of FinFETs and 256-Mb static random access memory (SRAM) cells were newly developed by featuring extreme ultraviolet (EUV). The intrinsic reliability mechanisms of 7-nm FinFET including hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric-breakdown (TDDB) are similar to that of the previous nodes, and would not be degraded by introducing the scaled FinFET. Moreover, we found that the use of EUV single patterning of middle of line (MOL) and back end of line (BEOL) improves reliability distribution remarkably as compared to the previous nodes using argon fluoride (ArF) multiple patterning techniques. We successfully demonstrated SRAM and logic high-temperature operating life (HTOL) up to 500 h, indicating the robustness of product-level reliability. These findings strongly suggest that the 7-nm technology featuring EUV is fully ready for high-volume manufacturing as well as providing a near future logic production with high-quality reliability.

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.

(Invited) Cluster-Preforming-Deposited Si-Rich W Silicide: A New Contact Material for Advanced CMOS

Reduction of electrical resistance of middle-of-line (MOL) is now a primary requirement for advanced CMOS. In this paper, we demonstrate that the cluster-preforming-deposited (CPD) WSi n (n ≤ 12) film is a promising contact material for S/D in CMOS; insertion of the WSi n film reduces the electron SBH to 0.32 eV at W/n-Si and to 0.43 eV at Co/n-Si junctions. This SBH reduction is due to the fact that the WSi n film has a low work function of 4.0 eV and effectively passivates the Si surface without forming an appreciable density of interface states, thereby releasing the Fermi level pinning at the Si surface. These junctions have an excellent stability against annealing up to 700˚C for W/WSi n /n-Si and to 500˚C for Co/WSi n /n-Si. Furthermore, this film significantly prevents the Cu diffusion with a TDDB barrier height of 1.33 eV under a 5 MV/ cm stress.

Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures

Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-Line (MOL) device parameters, is systematically investigated. It is concluded that the combined requirements of device electrostatics together with the demands on contact resistance, presents a Contacted-Gate-Pitch (CGP) scaling limit for horizontal-transport FETs. FET drive is expected to significantly degrade below this CGP ~ 40 nm as a result. Good agreement between hardware data and TCAD simulations is achieved and employed to estimate the contact resistance values for aggressively scaled FinFETs. These observations show that FinFETs scaled below CGP of 40 nm will require the contact resistivity (ρ C ) of ~8 × 10 -10 Ω-cm 2 , while fully ohmic contacts i.e., ρ C of ~1 × 10 -10 Ω-cm 2 will be required if FinFETs are to extend performance below CGP of 30 nm. Ultimately, transition to new device architectures in which contact area is independent of CGP and/or Fin-Pitch will be necessary.

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit’s lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology.

Yield Enhancement due to Addition of Bevel Cleans at Middle of Line(MOL) Zone

As the technology nodes become smaller and smaller the circuit dies get closer and closer to the edge of the wafer. Defects and issues on the bevel are seen to cause issues such as flaking and blocked plating on the dies at the edge of the wafer. This drastically increases the need for a clean wafer edge as the issues directly translate to yield loss at the end of the line. The wafer edge and backside are shown to have a significant impact on yield as well as process variation [1]. Introducing a dilute HF and SC1 bevel clean at the MOL layer resolves flaking and defect issues found on the bevel. Dispensing it on the backside of the wafer and ensuring that the chemistry is rolled over to the bevel results in the backside of the wafer becoming cleaner and helps resolve overlay issues. All the above stated effects are seen to result in an overall edge gain in edge yield.

Statistical evaluation method for lifetime distribution in field-accelerated time-dependent dielectric breakdown using two-step probability plot and multilink test scheme

A concept of a multilink test scheme with a two-step probability plot and its statistical accuracy of estimation are investigated for the time-dependent dielectric breakdown under defect clustering condition in the back end of line and middle of line. It is useful for obtaining an accurate estimation of lifetime that explains a complicated distribution shape due to impacts of clustered defects. Furthermore, applying a regression of the electric field dependence of breakdown to the lifetime distribution analysis will provide a more accurate estimation.

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Since 22nm technology node, FinFET technology is an attractive candidate for high-performance and power-efficient applications. This is achieved due to better channel control in FinFET devices obtained by wrapping a metal gate around a thin fin. In this paper, we investigate the detectability of bridge defects in FinFET based logic cells that make use of Middle-Of-Line (MOL) interconnections and multi-fin and multi-finger design strategies. The use of MOL to build the logic cells impacts the possible bridge defect locations and the likelihood of occurrence of the defect. Some defect locations unlikely to appear in planar CMOS now become more likely to occur due to the use of MOL. It is shown that these defects are difficult to be detected. The detectability of bridge defects has been analyzed for gates with different drive strengths and fan-in, and also extended to the different type of gates. A metric called Bridge Defect Criticality (BDC) is used to identify the most harmful bridge defects. This metric depends on the degree of detectability and likelihood of occurrence of a bridge defect. More design and/or test effort may be dedicated to those defects with higher a value of the BDC metric to improve product quality.

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict

Triple patterning lithography (TPL) is one of the most promising lithography technology in sub-14-nm technology nodes, especially for complicated low metal layer manufacturing. To overcome the intracell routability problem and improve the cell regularity, recently middle-of-line (MOL) layers are employed in standard cell design. However, MOL layers may introduce a large amount of cross-row TPL conflicts for row-based design. Motivated by this challenge, in this paper we propose the first TPL aware detailed placement toward zero cross-row MOL conflict. In standard cell precoloring, Boolean-based look-up table is proposed to reduce solution space. In detailed placement stage, three powerful techniques, i.e., local reordered single row refinement, min-cost flow-based conflict removal, and local cell interleaving, are proposed to provide zero TPL conflict solution. The experimental results demonstrate the effectiveness of our proposed methodologies.

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits

This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.

CMP: Consideration of Stop-on Selectivity in Advanced Node Semiconductor Manufacturing Technology

In advanced node semiconductor manufacturing, Chemical Mechanical Polish (CMP) is a critical integration step to many modules, from fin formation, replacement metal gate (RMG), to interconnects. In each application, CMP’s stop-on capability is increasingly seen as an essential element in gauging device integrity, and thus is critical to the successful implementation of a technology. Traditionally, CMP selectivity is merely a characteristic of slurry chemistry and its abrasive materials, and is measured by blanket rates of the corresponding films. However, in advanced node semiconductor manufacturing, as feature sizes are at Nano scale and polishing precision needs to be controlled at angstrom level, this slurry selectivity does not necessarily translate to a good stop-on capability. At this precision level, stop-on performance is sensitive to the selection of CMP pad as well as how the CMP process is developed. It is also highly sensitive to the integration process, including the deposition process and various integration steps leading to CMP. This presentation reviews the critical roles CMP plays in fin formation, replacement metal gate (RMG) and local interconnects. Taking middle of line (MOL) CMP steps as examples, detailed discussion will be presented on how selectivity is modulated and how the needs of stop-on capability is balanced with the need to make sure complete clearing.

Analysis for distribution network on hosting capacity of distributed wind turbines considering additional income under procedure conditions

An increasing number of wind turbines (WTs) are integrated into the distribution network to generate more electricity and reduce energy cost, which has a significant influence on the distribution network. So how to calculate the hosting capacity of WTs is of great importance. In this study, the analysis method was proposed to calculate the hosting capacity of WTs integrated into the distribution network under the procedure conditions. The authors firstly analysed several factors that imposed restrictions on the hosting capacity of the distribution network for WTs. Secondly, the authors built the optimisation model considering additional income, which aimed at reaching the maximum economic benefits by WT's access. Then the particle swarm optimisation algorithm, which could be applied to the problem, was given. In the calculation example, the authors analysed the different situation of WT's access to verify the proposed method. The installation points of WTs and the cost of investments were discussed to compare the economy of integration of WTs with the analysis results. The results showed that integrating WTs into the middle of lines could promote the economy and the decline in the cost of WTs also helped to enhance the hosting capacity of the distribution network for WTs.

Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing

In advanced technology nodes (sub 20nm), the gate & active contact architecture has become very complex. This architecture not only introduced new materials but also integrated additional patterning mask layers. This necessitated a separate Middle of Line (MoL) zone whereas conventionally contact integration used to be a Front End of Line (FEoL) process. This paper discusses wet cleaning challenges in MoL that were unforeseen with conventional contact architecture. Typical chemistries such as Sulfuric Peroxide Mixture (SPM), dilute Hydrofloric Acid (dHF), Aqua Regia, Standard Clean 1 (SC1), etc. that were used for contact cleaning or in salicidization process are found to be too aggressive due to smaller process window, shrinking Critical Dimensions (CD), and other challenges arising from overall tighter tolerances. As a result of device scaling, most of the MoL mask patterning is done with immersion lithography and double patterning techniques such as Litho-Etch Litho-Etch (LELE) are also needed. Immersion lithography is very sensitive to pre-litho backside and frontside particles which make pre-litho cleaning in MoL very critical as well. Also due to lack of high aspect ratio features in MoL (mostly contact holes), physical particle removal techniques such as droplet spray and MegaSonic can be very effectively used to achieve higher Particle Removal Efficiency (PRE). This paper summarizes such different scenarios & related challenges.

(Keynote) Challenges of 10 nm and 7 nm CMOS for Server and Mobile Applications

FINFET technology is now available on cutting edge mobile devices starting at the 16/14nm nodes. As the industry ramps toward 7nm, there will be intense pressure on density to counter the added cost driven by the adoption of more complex multiple patterning techniques for the FIN, Gate, various Middle Of Line (MOL)architectures, and Back End Of Line (BEOL) wiring levels. The need to reduce doping in the FINFETs will drive Multi-Work function solutions for same gate polarity. Likewise, the need for transistor performance will lead to new channel materials. Novel materials will be needed to reduce parasitic capacitance and resistance in the MOL and BEOL levels. Some incarnations of the 10nm node will be called "7nm" just as some variants of 20nm node were called 16/14, but the true "7nm" node circuit densities will require the next generation of lithography -- Extreme Ultra Violet (EUV) at 13.5nm wavelength. The key to adoption in the mobile space is the cost of the chip which is challenged by the need for novel cost intensive patterning techniques. The key to adoption in the server space will be ability to get more performance at constant chip power given the increased wiring parasitics. In all cases, novel materials will be needed to get to mature 7nm nodes.