Abstract
This paper presents a methodology for lifetime estimation of Front-End-of-Line (FEOL) and Middle-of-Line (MOL) time dependent dielectric breakdown (TDDB) in state-of-art logic circuits. The algorithm to extract vulnerable features of MOL-TDDB has been developed and implemented. A traditional 8-bit FFT circuit and a state-of-art Leon3 microprocessor are considered for lifetime calculation. The impact of different use scenarios on circuits is also investigated.
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