MHz Output Research Articles

A low-glitch binary-weighted DAC with delay compensation scheme

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current- steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable- delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transi- tions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 X termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respec- tively. The proposed DAC can be used in various appli- cations in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 lm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.

Fully Integrated Frequency Reference With 1.7 ppm Temperature Accuracy Within 0–80°C

A fully integrated 52 MHz frequency reference, designed in a 0.35 μm CMOS process, achieves 1.7 ppm frequency temperature accuracy within 0 to 80°C using a nonlinear compensation technique. The proposed low TC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> reference oscillator achieves the lowest reported uncompensated temperature coefficient, i.e., 65.25 ppm/°C, among the integrated frequency references. The output reference frequency is obtained by dividing the differential LC Colpitts oscillator output operating at 1.6 GHz. Oscillator core dissipates 14 mW from 2.5 V. The blocks related to the temperature compensation scheme and the remaining system blocks consume 3 mW and 165 mW from 3.3 V supply, respectively. The measured phase noise of 52 MHz output is -94 dBc/Hz at 10 kHz offset frequency and rms period jitter is 3.2 ps.

Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed. The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design. The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains. The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB. The measured SFDR at 1.7 MHz output signal is 58.91 dB, 58.53 dB and 56.98 dB for R/G/B channels, respectively. The DAC has good static and dynamic performance despite the single-ended output. The average rising time and falling time of three channels are 0.674 ns and 0.807 ns. The analog/digital power supply is 3.3 V/1.1 V. This triple-channel DAC occupies 0.5656 mm2.

State-of-the-art RF signal generation from optical frequency division

We present the design of a novel, ultralow-phase-noise frequency synthesizer implemented with extremely-low-noise regenerative frequency dividers. This synthesizer generates eight outputs, viz. 1.6 GHz, 320 MHz, 160 MHz, 80 MHz, 40 MHz, 20 MHz, 10 MHz and 5 MHz for an 8 GHz input frequency. The residual single-sideband (SSB) phase noises of the synthesizer at 5 and 10 MHz outputs at 1 Hz offset from the carrier are -150 and -145 dBc/Hz, respectively, which are unprecedented phase noise levels. We also report the lowest values of phase noise to date for 5 and 10 MHz RF signals achieved with our synthesizer by dividing an 8 GHz signal generated from an ultra-stable optical-comb-based frequency division. The absolute SSB phase noises achieved for 5 and 10 MHz signals at 1 Hz offset are -150 and -143 dBc/Hz, respectively; at 100 kHz offset, they are -177 and -174 dBc/Hz, respectively. The phase noise of the 5 MHz signal corresponds to a frequency stability of approximately 7.6 × 10(-15) at 1 s averaging time for a measurement bandwidth (BW) of 500 Hz, and the integrated timing jitter over 100 kHz BW is 20 fs.

Evaluation of Ultrasound Synthetic Aperture Imaging Using Bidirectional Pixel-Based Focusing: Preliminary Phantom and In Vivo Breast Study

In medical ultrasound imaging, lateral resolution is limited when using a fixed transmit focusing. Various synthetic aperture (SA) techniques, in which two-way dynamic focusing is enabled by utilizing prebeamformed radio-frequency (RF) data have been proposed for improving the spatial resolution. However, SA methods were not extensively evaluated in terms of their clinical performance. In this paper, a phantom and an in vivo evaluation of the SA method with bidirectional pixel-based focusing (BiPBF) is presented in comparison with the conventional beamforming. The performance of the proposed SA-BiPBF was assessed with a blind study and the established breast imaging-reporting and data system (BI-RADS), in addition to measuring contrast-to-noise ratio (CNR) and signal-to-noise ratio (SNR). Prebeamformed RF data were acquired from a tissue mimicking phantom (Model 040, CIRS Inc., Norfolk, VA, USA) and from patients with breast lesions by using a commercial ultrasound scanning system with a linear array transducer equipped with a research package and parallel data acquisition system (SonixTouch, SonixDAQ, and L14-5/38, Ultrasonix Corp., Canada). In phantom and in vivo experiments, a default setting of a breast preset was applied (e.g., the center frequency of 10MHz and acoustic output of MI = 0.66). In phantom experiment, the SA-BiPBF method showed higher CNR and SNR values compared to the conventional method (3.4 and 23.9dB versus 3.1 and 15.8dB, respectively). In addition, the lateral resolution and penetration depth were increased by 95.4% and 40.3%, respectively. Consistent with the phantom experiment, in the in vivo experiment with ten patients, the CNR value for the SA method was 3.3 ± 0.5 compared to 2.8 ± 0.8 for the conventional method. Similarly, the SNR values with the SA-BiPBF and conventional methods were 34.0 ± 3.6 and 27.2 ± 3.4dB, respectively. From the experiments, it was shown in side-by-side comparisons that the image quality of the SA-BiPBF method was considerably improved in both phantom and in vivo breast images. However, the SA-BiPBF image showed different features compared to the conventional one in the in vivo experiments. These features are resulting from the increased image quality of the SA-BiPBF method but are not always perceived as improvements by the radiologists.

A Passively Mode-Locked Erbium-Doped Fiber Laser Based on a Single-Wall Carbon Nanotube Polymer

We demonstrate a simple, compact and low-cost mode-locked erbium-doped fiber laser (EDFL) using a single-wall carbon nanotube (SWCNT) poly-ethylene oxide (PEO) composite as a passive saturable absorber (SA). The composite with an SWCNT concentration of 18wt% is prepared by mixing the SWCNT homogeneous solution with a diluted PEO polymer solution. A droplet of the polymer composite is applied on the fiber ferrule end, which is then mated to another clean ferrule connector to construct an SA. The SA is then integrated into the laser system to self-start stable mode locking at 1557 nm without employing a polarization controller. The EDFL generates a stable soliton pulse train with a duration of 0.81 ps, repetition rate of 44 MHz and average output power of 92.4 μW at a 980 nm pump power of 26.8 mW. The soliton laser starts to lase at a pump power threshold of 14.6 mW.

New design approach of FPGA based control system and implementation result in KSTAR

The frequency modulation (FM) reflectometer in KSTAR is under commissioning to measure the electron density profile which focused on edge area of plasma. This diagnostic system generated order of tens MHz output signal from an intermediate frequency (IF) amplifier after a radio frequency (RF) mixer. An arbitrary waveform generator is also required for triggering a fast frequency sweep source. We have developed a data acquisition system with multi-functions which composes several digitizers and waveform generator for KSTAR reflectometer. Along with this typical hardware system, we have newly developed a field programmable gate array (FPGA) based signal controller. This customized board adapts FPGA Mezzanine Card (FMC) as a daughter board within single package of 3U Compact PCI form factor. We have been evaluating Experimental Physics and industrial control system (EPICS) input output controller (IOC) over an embedded PowerPC processor on several customized hardware. Using previous result of investigation, this new processor embedded digitizer supports full function of EPICS including KSTAR standard software framework.

A low glitch 12-bit current-steering CMOS DAC for CNC systems

A 12-bit, 100-MHz CMOS current-steering D/A converter for CNC (computer number control) systems is presented. To reduce the glitch and increase the SFDR (spurious-free dynamic range), a low crosspoint switch driver and a special dummy switch are applied. In addition, a 4-5-3 segmental structure is used to optimize the performance and layout area. After improvement, the biggest glitch energy decreased from 6.7 pVs to 1.7 pVs, the INL decreased from 2 LSB to 0.8 LSB, the SFDR is 78 dB at a 100-MSPS clock rate and 1 MHz output frequency. This DAC can deliver up to 20.8 mA full-scale current into a 50 Ω load. The power when operating at full-scale current is 163 mW. The layout area is 1.8 × 1.8 mm2 in a standard 0.35-μm CMOS technology.

A low jitter PLL clock used for phase change memory

A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

325 MHz and near transform-limited pulse output directly from an Er:fiber ring laser

A compact Er:fiber ring laser operated at a fundamental repetition rate of 325 MHz is reported. Two gain fibers with opposite dispersion are employed to shorten the fiber laser cavity for high repetition rate and soliton-like pulse generation without losing gain and compactness. The spectral bandwidth of the output pulse is 24 nm and the direct pulse duration is 123 fs without extra-cavity compression, which are values near the transform-limited range.

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers. A brief comparison between current-commutating passive mixers and active mixers is presented. The effect of source and load impedance on the linearity of a mixer is analyzed. Specially, the impact of the input impedance of the transimpedance amplifier (TIA), which acts as the load impedance of a mixer, is investigated in detail. The analysis is verified by a passive mixer implemented with 0.18 μm CMOS technology. The circuit is inductorless and can operate over a broad frequency range. On wafer measurements show that, with radio frequency (RF) ranges from 700 MHz to 2.3 GHz, the mixer achieves 21 dB of conversion voltage gain with a −1 dB intermediate frequency (IF) bandwidth of 10 MHz. The measured IIP3 is 9 dBm and the measured double-sideband noise figure (NF) is 10.6 dB at 10 MHz output. The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.

Voltage-Mode Four-Phase Sinusoidal Generator and Its Useful Extensions

This paper introduces a new voltage-mode second-order sinusoidal generator circuit with four active elements and six passive elements, including grounded capacitors. The frequency and condition of oscillation can be independently controlled. The effect of active element’s nonidealities and parasitic effects is also studied; the proposed topology is good in absorbing several parasitic elements involved with the active elements. The circuit is advantageous for generating high frequency signals which is demonstrated for 25 MHz outputs. Several circuit extensions are also given which makes the new proposal useful for real circuit adoption. The proposed theory is validated through simulation results.

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160MHz output and 22.5° for the 320MHz output. The radiation-hard design, integrated in a 130nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.

A 12-Bit 1GS/s Current-Steering DAC with Matching Capacitor in Switched Current Cell

This paper presents a 12-bit 1GS/s current-steering DAC with matching capacitor in switched current cell, which has been designed to enhance the DAC’s dynamic performance. Compared with traditional designs, the switched current cell with an matching capacitor can suppress the output-dependent delay differences effect. The Chip was designed by using TSMC 0.18μm CMOS mixed model, and the post-simulation results show that the DAC achieves 74.1 and 68.9 dBc SFDR at 1GS/s with 50MHz and 450MHz output frequency, respectively.

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.

Low intensity ultrasound stimulates osteoblast migration at different frequencies

This study investigated the effects of different frequencies of low intensity ultrasound on osteoblast migration using an in vitro scratch-wound healing assay. Mouse calvarial-derived MC3T3-E1 osteoblasts in culture were exposed to continuous 45kHz ultrasound (25mW/cm(2)) or pulsed 1MHz ultrasound (250mW/cm(2)) for 30min followed by 2days' culture. Ultrasound treatment with either kHz or MHz output similarly and significantly increased cell numbers after 2days in culture compared with untreated control cultures. In the scratch-wound healing assay the presence of the cell proliferation inhibitor mitomycin C (MMC) did not influence scratch-wound closure in control cultures indicating that cell migration was responsible for the in vitro wound healing. Application of ultrasound significantly stimulated wound closure. MMC did not affect kHz-stimulated in vitro wound healing; however, MMC reduced in part the scratch-wound closure rate in MHz-treated cultures suggesting that enhanced cell proliferation as well as migration was involved in the healing promoted by MHz ultrasound. In conclusion, both continuous kHz and pulsed MHz ultrasound promoted osteoblastic migration; however, subtle differences were apparent in the manner the different ultrasound regimens enhanced in vitro scratch-wound healing.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is −120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is −169 dBc/Hz.

The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase- locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively

High Efficiency 500W RF Generator

In the previous literature about RF generator, Efficiency of output of RF generator can reach 60-70 percent. In this paper, a new 500W RF generator with high efficiency and high stability is designed and fabricated for plasma applications. The efficiency of a power amplifier in the RF generator is improved by using Class-E amplifier. The Class-E power amplifiers described here is based on a load network synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the AC cycle. For that circuit, the author measures 73 percent efficiency of output of RF generator at 13.56MHZ and 478W output from DE375 MOSFET. The main reasons of power dissipation mainly are analyzed, and some measures are taken to improve them by the optimization principles and experimental results and the efficiency of the power output can reach above 70 percent.

Power efficient high-speed DAC for wideband communication applications

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 + 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion step*W).