A low-glitch binary-weighted DAC with delay compensation scheme

Abstract

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current- steering digital-to-analog converter (DAC). Instead of using large input buffers to drive a lot of current switches and re-timing latches, the proposed design uses variable- delay buffers with a compact layout to compensate for the delay difference among different bits, and to reduce glitch energy from 132 to 1.36 pV s during major code transi- tions. The measured spurious free dynamic range (SFDR) has been improved over 10 dB, as compared to DACs without variable-delay buffers. At 250 MS/s update rate, the proposed DAC achieves 56 dB SFDR for 0.67 MHz output frequency and 49 dB SFDR for 94 MHz output frequency with 50 X termination. For static performance, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) is less than 1.6 and 1.8 LSB, respec- tively. The proposed DAC can be used in various appli- cations in industry, including digital video, digital TV, wireless communication system, etc. This chip was implemented in TSMC 1P6M 0.18 lm CMOS technology and dissipates 19 mW from a single 1.8 V power supply.