Metal-ferroelectric-insulator-semiconductor Field-effect Transistor Research Articles

A model for the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

An improved theoretical model on the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) has been proposed by considering the history-dependent electric field effect and the mobility model. The capacitance–voltage (C–V) characteristics of MFIS structure is evaluated by combining the switching physics of ferroelectric with the silicon physics, and the drain current-gate voltage (ID-VGS) and drain current-drain voltage (ID-VDS) characteristics of MFIS-FET are modeled by combining the switching physics of ferroelectric with Pao and Sah’s double integral. For two MFIS-FETs with SrBi2Ta2O9 and (Bi,La)4Ti3O12 ferroelectric layers, the C–V, ID-VGS and ID-VDS characteristics are simulated by using the improved model, and the results are more consistent with the previous experiment than those based on Lue model, indicating that the improved model is suitable for simulating the electrical characteristics of MFIS-FET. This work is expected to provide some guidance to the design and performance improvement of MFIS structure devices.

Modeling of MFIS-FETs for the Application of Ferroelectric Random Access Memory

It is recognized that the conventional model for metal-ferroelectric-insulator-semiconductor field-effect transistors (MFIS-FETs) always neglects the history-dependent electric field effect of the ferroelectric layer. In this paper, an improved model combining the dipole switching theory with the silicon physics of metal-oxide-semiconductor structures and with Pao and Sah's double integral, respectively, is proposed to describe the capacitance-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) characteristics of MFIS structures and the drain current-gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and drain current-drain voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) characteristics of MFIS-FETs. Close agreement between modeling and experimental results confirms the validity of the improved model. The influence of the gate voltage, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer thickness, and interface layer thickness on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> , and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics are simulated and discussed. The memory windows of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristics, as well as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> characteristics, increase with increasing gate voltage. The thicker the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or interface layer, the worse the transistor characteristics. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the mathematical description can be easily combined with electronic design automation software for circuit simulation.

Interface effects on the characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

The interface effects on the electrical characteristics of metal-ferroelectric-insulator- semiconductor field-effect transistor (MFIS-FET) are studied using an improved model in which the expressions for interface and the mobility model are incorporated into Lue model. The interface layer between the ferroelectric and the electrode and the SiO2 layer between the insulator and the semiconductor have been investigated. Capacitance–gate voltage (C–VG) and drain current–gate voltage (ID–VGS) characteristics are modeled with fixed interface layer and SiO2 layer thicknesses and show good agreement with the experiments, verifying the validity of the improved model and the existence of the interface in the transistor. The characteristics, such as C–VG, ID–VGS and drain current–drain voltage (ID–VDS), are modeled respectively with various interface layer and SiO2 layer thicknesses. The thicker the interface layer and SiO2 layer are, the worse the transistor characteristics become. Similar characteristics can be observed at the specific thickness of the two layers, indicating that both interface layer and SiO2 layer should be considered when the characteristics of MFIS-FETs degrade. In addition, the type of the interfaces can be distinguished by comparing the capacitance in the accumulation region. It is expected that this work can offer some useful guidance to the design and performance improvement of MFIS structure devices.

Electrical properties of metal-ferroelectric-insulator-semiconductor field effect transistors (MFIS-FETs) using the polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE))/ZrO2/Si structure

In this study, we fabricated the n-channel metal-ferroelectric-insulator-semiconductor field effect transistors (MFIS-FETs) using an Au/polyvinylidene fluoride-trifluoroethylene P(VDF-TrFE)/ZrO2/Si(100) structures. The ZrO2 thin film had the equivalent oxide thickness (EOT) value of around 9 nm. And the P(VDF-TrFE) film on a ZrO2/Si structure showed good ferroelectric property with memory window width of 2.5 V for a bias voltage sweeping of ±7 V. The leakage current density of this MFIS structure showed very excellent insulation property with about 9 × 10−8 A/cm2 at 5 V. Based on these results, we fabricated and investigated MFIS-FETs with ferroelectric polymer P(VDF-TrFE) film and ZrO2 buffer layer. The memory window width and on/off ratio of the MFIS-FET was about 4.5 V and 103, respectively. These results predicted that the P(VDF-TrFE) thin film would be useful for the realization of 1-transistor type ferroelectric memory.

Fabrication and Characterization of MFIS-FET Using Au/BLT/LZO/Si Structures

We fabricated the n-channel metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) using an Au/(Bi,La) 4 Ti 3 O 12 /LaZrO x /Si(100) gate structure. We observed that the LaZrO x thin film had the equivalent oxide thickness value of around 8.7 nm. The 420-nm-thick (Bi,La) 4 Ti 3 O 12 film on a LaZrO x /Si structure, showed a good ferroelectric property and had the width of the memory window of 1.2 V for a bias voltage sweeping of ± 7 V. The drain current-gate voltage (I D -V G ) of an Au/(Bi,La) 4 Ti 3 O 12/ LaZrO x /Si(100) MFIS-FET showed threshold voltage shift (memory window width) owing to the ferroelectric (Bi,La) 4 Ti 3 O 12 film. The drain current-drain voltage (I D -V D ) characteristic curves exhibit typical n-channel field-effect transistor current-voltage characteristic. However, relatively large leakage current observed in the I D –V G and the I D –V D characteristic curves, might be caused by the high density of pores in the BLT film.

The effect of band offset on the retention properties of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (Dy2O3,Y2O3)-semiconductor capacitors and field effect transistors

Metal-ferroelectric-insulator-semiconductor field effect transistors (MFISFETs) and capacitors with the structures of Al∕Pb (Zr0.53,Ti0.47) O3 (PZT)∕Dy2O3∕Si and Al∕PZT∕Y2O3∕Si were fabricated. The variation of the memory window as a function of annealing temperature was studied. The maximum capacitor-voltage (C-V) memory window of Al∕PZT∕Dy2O3∕Si capacitors was 2.95V. The retention times of Al∕PZT∕Y2O3∕Si and Al∕PZT∕Dy2O3∕Si MFISFETs were 11.5days and 11.1h, respectively. The longer retention time of Al∕PZT∕Y2O3∕Si MFISFETs is attributed to the larger conduction band offset at the Y2O3∕Si interface (2.3eV) compared to that of Dy2O3∕Si (0.79eV).

MULTI-BIT PROGRAMMING TECHNIQUE FOR AN MFIS-FET WITH A Pt/(Bi, Nd)4 Ti3O12/HfO2/Si SUBSTRATE STRUCTURE

ABSTRACT In this paper, we describe a multi-bit programming technique for a metal-ferroelectric-insulator-semiconductor field-effect-transistor (MFIS-FET) to increase the memory capacity of ferroelectric random access memory (FeRAM). We fabricated a p-channel MFIS-FET using (Bi, Nd)4Ti3O12 film as a ferroelectric and HfO2 film as an insulator. The multi-bit data is programmed by controlling the local polarization (minor loop) of three regions of the ferroelectric layer in the channel of the MFIS-FET. We controlled the polarizations of the ferroelectric film near the source, near the channel, and near the drain regions by separately applying programming pulses to the gate, source, drain, and Si substrate, which changed the threshold voltage and drain current of the MFIS-FET. In this study, two-bit data are programmed in one MFIS-FET, and drain currents corresponding to data “0”, “1”, “2”, and “3” are obtained.

FORMATION OF (Bi,La)4Ti3O12 FILMS ON Si(100) SUBSTRATES USING ZrO2 BUFFER LAYERS

ABSTRACT The ferroelectric behavior of (Bi,La)4Ti3O12 (BLT) films deposited on Si(100) substrates with the use of ZrO2 buffer layers was demonstrated. ZrO2 films were prepared using the sol-gel method. Then, they were subjected to dry O2 annealing in a rapid-thermal-annealing furnace. BLT films were deposited on these structures through the sol-gel method, and they were characterized through X-ray diffraction analysis and atomic-force microscopy. It was found from capacitance-voltage measurements that the BLT films had a hysteresis loop and that the memory window was about 2 V for the voltage sweep of ±5 V. Based on these results, it can be concluded that the use of the BLT/ZrO2/Si(100) structure in the fabrication of MFISFETs (metal-ferroelectric-insulator-semiconductor field-effect transistors) holds great promise.

Memory operation of Pt–SrBi 2Ta 2O 9–Y 2O 3–Si field-effect transistor with damage-free selective dry etching process

Metal–ferroelectric–insulator–semiconductor field-effect transistor (MFISFET) with Pt–SrBi 2Ta 2O 9 (SBT)–Y 2O 3–Si gate structure was fabricated with a selective dry etching of SBT and Y 2O 3. The etching characteristics of SBT, Y 2O 3, and silicon were investigated with various Ar/Cl 2 gas mixing ratios. Inductively coupled plasma (ICP) Powers, and RF bias powers and the surface condition after the etching was analyzed by using the scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoemission spectroscopy (XPS), and Rutherford back scattering (RBS) measurement. The etch-stop process was successfully achieved at the condition of 50% Cl 2 concentration with the ICP power of 900 W and the RF bias power of 100 W where the selectivity of SBT to Y 2O 3 was 4. The fabricated MFISFET with the etch-stop process showed good memory operation with 1.2 V threshold voltage difference and more than three orders of drain current difference in the on/off drain current ratio at the operating voltage of 7 V. These results meant that the etch-stop process was successfully carried out and applied to MFISFET fabrication without degradation of the ferroelectric characteristics and damage on silicon surface.

Fabrication of MFISFETs with Pt/SrBi2Ta2O9/Y2O3/Si gate structure by developing an etch-stop process

A metal–ferroelectric–insulator–semiconductor field-effect transistor (MFISFET) was fabricated with an etch-stop process based on the selectivity between SrBi2Ta2O9 (SBT) and Y2O3. Depending on the selectivity with various Ar/Cl2 gas mixture, we could find the acceptable thickness of Y2O3 for a successful etch-stop process. The electrical characteristics of the MFISFET fabricated with the developed etch-stop process showed no damage of the silicon surface of source/drain regions, resulting in good ferroelectric memory characteristics and programmable operation. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Application of Metal-Ferroelectric-Insulator-Semiconductor Field-Effect Transistors (MFISFETs) in Non-Volatile Logic Integrated Circuits

New concept of non-volatile logic integrated circuit system using MFISFETs is proposed first in this paper, in which information in CMOS digital circuits can be protected from accidental or planned power outages and restored after the power recovers. The basic operation of the proposed system has been ascertained using Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. A HSPICE macro model of Metal- Ferroelectric-Insulator-Semiconductor Field-Effect Transistors (MFISFETs) using Schmitt trigger model is created and applied to the circuit simulation to test its validity. The states of logic nodes in the volatile CMOS digital circuits can be stored onto corresponding MFISFETs when power shuts off abruptly and be restored immediately when power-failure recovers, thus the whole system continues to work as if no power outrage had happened. As a result, the nonvolatile logic function is realized with MFISFETs and the feasibility of application in VLSI digital systems is demonstrated.

Novel Multilevel Non-Destructive-Read-Out (NDRO) Ferroelectric Floating-Gate Random Access Memory (FFRAM)

Novel multilevel non-destructive-read-out FFRAM is proposed in this paper, in which data more than one bit can be stored in a metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) memory cell to increase bit-area property. Given the same storage capacity, the number of cells in multilevel FFRAM decreases significantly compared with current FFRAM, thus chip area and power consumption are reduced accordingly. An original multilevel NDRO FFRAM cell is proposed, in which multi-bit binary data can be stored into a selected cell of the memory array and be read out correctly. A HSPICE macro model of metal-ferroelectric-insulator-semiconductor field-effect transistors (MFISFETs) using cascade Schmitt trigger model is created for simulating saturated and unsaturated hysteresis loops. Realization of a multilevel NDRO FFRAM cell and the structure of the memory array are discussed. The timing sequence of the “write”, “read” as well as “clear” operation is also investigated. A 4× 4 memory array with A/D converters as I/O is presented in the end.

Effects of annealing temperatures on the electrical properties of pulsed laser deposited Bi 3.25La 0.75Ti 3O 12 thin films for field effect transistor-type memory device

Electrical characterizations of a metal-ferroelectric-insulator-semiconductor field effect transistor (MFISFET) using Au/Bi 3.25La 0.75Ti 3O 12/Si 3N 4/Si(1 1 1) were investigated by studying the effects of the annealing conditions. Ferroelectric Bi 3.25La 0.75Ti 3O 12 (BLT) was prepared on 15 nm Si 3N 4 coated p-type Si(1 1 1) substrates by the pulsed laser deposition method at a deposition temperature of 400 °C and an oxygen pressure of 200 m Torr. The crystalline structures showed polycrystalline films with preferable c-axis orientations at higher annealing temperatures. The capacitance–voltage ( C– V) measurements for the as-deposited films, 600 and 700 °C annealed films showed a decreasing memory window value of 1.31, 0.78, and 0.36 V, respectively. The generation of low coercive values for higher annealed films is known to be the main cause for such results.

Retention Characteristics of (Bi,La)4Ti3O12 Films on Si(100) Substrates Using LaAlO3 Buffer Layers

We demonstrate the ferroelectric behavior of (Bi,La)4Ti3O12 (BLT) films deposited on Si(100) substrates by using LaAlO3 buffer layers. LaAlO3 films were prepared by molecular beam deposition method. Then, they were subjected to ex situ dry N2 annealing in a rapid thermal annealing furnace. From the capacitance-voltage measurement, the dielectric constant of LaAlO3 was estimated to be 20 to 26. On these structures, BLT films were deposited by sol-gel method and they were characterized by X-ray diffraction analysis. It was found from capacitance-voltage measurements that the characteristics showed a hysteresis loop and the memory window was about 0.5 V for the voltage sweep of ±9 V. It was also found from the retention measurement that the higher and lower capacitance values in the hysterisis loop could be distinguished at least for 3 days. It is concluded from these results that the BLT/LaAlO3/Si(100) structure is one of the most promising structures for realizing MFISFETs (metal-ferroelectric-insulator-semiconductor field effect transistors).

Device modeling of ferroelectric memory field-effect transistor for the application of ferroelectric random access memory.

An improved theoretical analysis on the electrical characteristics of ferroelectric memory field-effect transistor (FeMFET) is given. First, we propose a new analytical expression for the polarization versus electric field (P-E) for the ferroelectric material. It is determined by one parameter and explicitly includes both the saturated and nonsaturated hysteresis loops. Using this expression, we then examine the operational properties for two practical devices such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) as well. A double integral also has been used, in order to include the possible effects due to the nonuniform field and charge distribution along the channel of the device, to calculate the drain current of FeMFET. By using the relevant material parameters close to the (Bi, La)4Ti3O12 (BLT) system, accurate analyses on the capacitors and FeMFET's at various applied biases are made. We also address the issues of depolarization field and retention time about such a device.

Electrical characteristics of SrxBi2.4Ta2O9 thin film and Pt/Sr0.85Bi2.4Ta2O9/Al2O3/Si structure

SrxBi2.4Ta2O9 (0.7 ≤ x ≤ 1.3) thin films were processed by metalorganic decomposition and their ferroelectric characteristics were investigated. The Sr-deficient SrxBi2.4Ta2O9 films exhibited well-developed ferroelectric hysteresis curves compared to those of the Sr-excess films, and Sr0.85Bi2.4Ta2O9 film had the optimum electrical characteristics among SrxBi2.4Ta2O9 films. Electrical characteristics of the Pt/SBT/Al2O3/Si structure using Sr0.85Bi2.4Ta2O9(SBT) film were investigated for metalferroelectric-insulator-semiconductor field-effect-transistor (MFIS-FET) applications. Memory window of C-V hysteresis characteristics of the Pt/SBT/Al2O3/Si structure became large with decreasing the Al2O3 thickness, and the Pt/SBT(400 nm)/Al2O3 (10 nm)/Si structure gave memory window of 2.2 V at sweeping voltages of ±5 V. The Pt/SBT/Al2O3/Si structure can be proposed for MFIS-FET applications.

Device modeling of ferroelectric memory field-effect transistor (FeMFET)

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.

Study of ferroelectric-thin-film thickness effects on metal-ferroelectric-SiO2–Si transistors

This article examines the thickness effects of ferroelectric films on gate tunneling suppression and charge control in metal-ferroelectric-insulator-semiconductor field-effect transistors (MFISFETs). The formalism used is based on a blocking-layer model for the ferroelectric film and a self-consistent solution of the Poisson and Schrödinger equation. We show that with a polar ferroelectric the threshold voltage of the FET can be altered by controlling the ferroelectric film thickness. We also study the thickness dependence of the capacitance–voltage curve and the surface charge density and the effects of ferroelectric hysteresis. The tunneling probability and leakage current calculation in a MFISFET device are provided in this article. Ferroelectrics-based transistors show higher sheet charges and lower tunneling currents than oxide-based devices.

Fabrication of Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Using Mo/Pb(Zr,Ti)O 3 /ZrTiO 4 /Poly Si Thin Film Structure

In this work, metal/ferroelectric/insulator/semiconductor field effect transistors (MFISFET) using Mo/Pb(Zr,Ti)O 3 (PZT)/ZrTiO 4 (ZT)/polycrystalline Si (poly-Si) thin film structures were fabricated and characterized for nonvolatile nondestructive read-out (NDRO) memory devices. The 300 nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO 4 (50 nm)/Si substrates. After annealing process at 600 for crystallization of PZT thin films, there was no inter-diffusion of Pb and Si. C-V hysteresis was observed in Pt/PZT/ZrTiO 4 /Si (MFIS) structures. For fabricating memory device, we used thin film transistor (TFT) with poly-Si thin film. The amorphous Si thin films on SiO 2 substrates were crystallized by MILC (Metal Induced Lateral Crystallization) method at low temperature as 550 . The drain current-gate voltage (I D -V G ) characteristics of MFISFET using the Mo/PZT/ZrTiO 4 /poly-Si thin film structures showed threshold hysteresis due to the ferroelectric property of the PZT thin films. The threshold hysteresis value, i.e. memory window was about 0.6 V in the applied gate voltage range of 5 V, and almost same as C-V hysteresis value in MFIS structure.

Fabrication of Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Using Mo/Pb(Zr,Ti)O 3 /ZrTiO 4 /Poly Si Thin Film Structure

In this work, metal/ferroelectric/insulator/semiconductor field effect transistors (MFISFET) using Mo/Pb(Zr,Ti)O 3 (PZT)/ZrTiO 4 (ZT)/polycrystalline Si (poly-Si) thin film structures were fabricated and characterized for nonvolatile nondestructive read-out (NDRO) memory devices. The 300 nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO 4 (50 nm)/Si substrates. After annealing process at 600 for crystallization of PZT thin films, there was no inter-diffusion of Pb and Si. C-V hysteresis was observed in Pt/PZT/ZrTiO 4 /Si (MFIS) structures. For fabricating memory device, we used thin film transistor (TFT) with poly-Si thin film. The amorphous Si thin films on SiO 2 substrates were crystallized by MILC (Metal Induced Lateral Crystallization) method at low temperature as 550 . The drain current-gate voltage (I D -V G ) characteristics of MFISFET using the Mo/PZT/ZrTiO 4 /poly-Si thin film structures showed threshold hysteresis due to the ferroelectric property of the PZT thin films. The threshold hysteresis value, i.e. memory window was about 0.6 V in the applied gate voltage range of 5 V, and almost same as C-V hysteresis value in MFIS structure.