Abstract
Novel multilevel non-destructive-read-out FFRAM is proposed in this paper, in which data more than one bit can be stored in a metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) memory cell to increase bit-area property. Given the same storage capacity, the number of cells in multilevel FFRAM decreases significantly compared with current FFRAM, thus chip area and power consumption are reduced accordingly. An original multilevel NDRO FFRAM cell is proposed, in which multi-bit binary data can be stored into a selected cell of the memory array and be read out correctly. A HSPICE macro model of metal-ferroelectric-insulator-semiconductor field-effect transistors (MFISFETs) using cascade Schmitt trigger model is created for simulating saturated and unsaturated hysteresis loops. Realization of a multilevel NDRO FFRAM cell and the structure of the memory array are discussed. The timing sequence of the “write”, “read” as well as “clear” operation is also investigated. A 4× 4 memory array with A/D converters as I/O is presented in the end.
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