Metal Oxide Semiconductor Technology Research Articles

Performance of MOS Capacitor with Different Dielectric Material Simulated Using Silvaco TCAD Tools

Metal oxide semiconductor (MOS) capacitor is a trilayer device that comprises of metal, dielectric, and semiconductor layer. The advancement of MOS technology has greatly give huge improvement to MOS devices which lead to scaling down the MOS devices. The reduction of dielectric thickness of conventional dielectric material has coming to an end, therefore as alternative new material with high mobility carrier is suggested to overcome the problem. The objectives of this work are to study the performance of MOS capacitor. Two parameters were varied, first the semiconductor material which is silicon (Si), germanium (Ge) and silicon germanium (SiGe) and second is the dielectric material that is silicon dioxide (SiO2) and silicon nitride (Si3N4). The performance of the MOS capacitor is evaluated based on the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. Silvaco TCAD tool were use as as simulation tool for the method of investigation. Result shown that the performance of the MOS capacitor increased when Ge and SiGe were used as semiconductor material and Si3N4 as dielectric layer. It can see that with VT of 4.15 V for MOS with Ge and 4.28 V for MOS with SiGe. For the C-V properties Cmax value for both devices are F and F, respectively. The results show that there is around 100% increment in capacitance value when Ge is used as semiconductor layer but there is no increment or decrement in capacitance value when SiGe is used. Based on the obtained results, Ge is chosen as the best semiconductor material.

Heterogeneous Integration of Atomically-Thin Indium Tungsten Oxide Transistors for Low-Power 3D Monolithic Complementary Inverter.

In this work, the authors demonstrate a novel vertically-stacked thin film transistor (TFT) architecture for heterogeneously complementary inverter applications, composed of p-channel polycrystalline silicon (poly-Si) and n-channel amorphous indium tungsten oxide (a-IWO), with a low footprint than planar structure. The a-IWO TFT with channel thickness of approximately 3-4 atomic layers exhibits high mobility of 24 cm2 V-1 s-1 , near ideally subthreshold swing of 63mV dec-1 , low leakage current below 10-13 A, high on/off current ratio of larger than 109 , extremely small hysteresis of 0mV, low contact resistance of 0.44 kΩ-µm, and high stability after encapsulating a passivation layer. The electrical characteristics of n-channel a-IWO TFT are well-matched with p-channel poly-Si TFT for superior complementary metal-oxide-semiconductor technology applications. The inverter can exhibit a high voltage gain of 152V V-1 at low supply voltage of 1.5V. The noise margin can be up to 80% of supply voltage and perform the symmetrical window. The pico-watt static power consumption inverter is achieved by the wide energy bandgap of a-IWO channel and atomically-thin channel. The vertically-stacked complementary field-effect transistors (CFET) with high energy-efficiency can increase the circuit density in a chip to conform the development of next-generation semiconductor technology.

(Invited) Investigating Defects in the High-k/Ingaas System at Cryogenic Temperature

III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature.The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data.In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled ‘border traps’) and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results.Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures.[1] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” John Wiley & Sons, New York, 1982.[2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997).[3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020)[4] G. Sereni, et al. “IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder's design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

Distinct ρ-based model of silicon N-channel double gate MOSFET

<span lang="EN-US">Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results.</span>

The Birth of the Microprocessor

The story starts in February 1968 when I joined Fairchild Semiconductor R&D Lab in Palo Alto, CA, USA. At that time, nearly all the integrated circuits (ICs) in production used bipolar technology. Metal–oxide–semiconductor (MOS) technology was up-and-coming but still had many problems: it was extremely slow and was not yet reliable. I believed that the future of digital electronics belonged to MOS technology because one could integrate in the same silicon area ten times more logic gates with half the number of manufacturing steps required by bipolar technology.

Online Nonlinear Error Compensation Circuit Based on Neural Networks

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.

Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)

Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400[Formula: see text]MHz to 405[Formula: see text]MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680[Formula: see text]mV supply voltage in 45[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from [Formula: see text]0.422[Formula: see text]V to [Formula: see text][Formula: see text]V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495[Formula: see text]MHz at 0.68[Formula: see text]V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402[Formula: see text]MHz, thus making it better suitable for the MICS band of applications. Phase noise of [Formula: see text][Formula: see text]dBc/Hz at an offset of 200[Formula: see text]kHz was obtained. The proposed differential DCO consumed power was 95.26[Formula: see text][Formula: see text]W. The figure of merit (FoM) for this DCO is [Formula: see text] (dBc/Hz). The area consumed by the DCO is 0.01872[Formula: see text]mm2.

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

Relationship between ion track characteristics and single event transients in nanometer inverter chain

Ions with the same linear energy transfer (LET) value, but different energies and species have various ion track characteristics, and thus induce different single event transient (SET) responses in combinational logics. As the technology feature size shrinks, this issue continues to be serious. The research of the relationship between ion track characteristics and SETs in the nanometer combinational logic circuits is of great significance for accurately predicting the soft error rates of nanometer devices used in spacecraft. The combinational logic circuit investigated in this paper is a 65 nm bulk silicon complementary metal oxide semiconductor (CMOS) technology inverter chain. The three-dimensional TCAD model of the inverter chain is established, and the particle transport program for the ion track in bulk silicon is developed by Geant4. The track characteristics of high- and low-energy ions (the energy of low-energy ions is less than 10 MeV·n<sup>–1</sup>, the energy of high-energy ions ranges from tens of MeV·n<sup>–1</sup> to hundreds of MeV·n<sup>–1</sup>) which have the same LET value are compared with each other. Based on the coupled simulation of TCAD and Geant4, the difference in SET pulse widths, induced by ions with the same LET value but different energies, are investigated. It is found that when the energy per nucleon ratio of high-energy ion to low-energy ion increases, the difference in electron-hole pair densities near the center axis of the ion track is more significant, and thus the difference in SET pulse widths is larger. If the energy per nucleon ratio is similar, raising the LET value of ions can increase the difference in electron-hole pair densities on the same radial scale of the ion tracks, and make the SET pulse width difference more obvious. For the high- and low-energy ions with the same LET value, the single event charge generations are different. On the other hand, the change of the ion incident angle results in different charge collections. The coupling of these two factors makes the difference in SET pulse widths dependent on the incident angle of ions. In addition, the influence of ion track characteristics on SET has a weak correlation with the bias voltage of the inverter chain.

Near-zero computing using NCFET for IoT applications

The energy consumption of the devices or circuits built on the IoT's is becoming a significant concern with the complementary metal oxide semiconductor (CMOS) technology scaling. To reduce energy consumption, supply voltage (VDD) scaling has proved to be an effective technique with near-threshold/subthreshold computations depicting the endpoint of voltage scaling. This paper discusses how the near-zero computing (NZC) is achieved by scaling the VDD beyond the subthreshold regime using the negative capacitance FET (NCFET) to enable IoT with beyond CMOS features. After characterising the NCFET for near zero operation, the basic computational circuits: logic gates and 1-bitfull adder circuit are designed and simulated using NCFET at near-zero VDD of 0.1 V. In comparison with the CMOS counterparts, the NCFET logic designs have achieved significant improvements and is found that the NCFET logic results in more than 54%, 68%, 85%, and 95% savings in power, delay, energy, and EDP respectively.

Effect of Statistical Dopant Fluctuations on Threshold Voltage of Emerging Devices

This paper presents a comparative study on the effect of statistical dopant fluctuations on threshold voltage (Vth) of emerging and conventional metal-oxide-semiconductor (MOS) field-effect (FET) transistors (MOSFETs). In this context, three n-channel MOSFET structures representing three different complementary MOS (CMOS) technologies at the 20 nm node are considered. The structures represent a conventional device with symmetric halo or pocket regions around the n+source-drain formed by a single p-type dopant implantation; a second conventional device with symmetric p-type halo regions around the n+source-drain formed by multiple p-type dopant implantations; and an emerging epitaxial-channel device with symmetric p-type halo regions around the n+source-drain where the halo regions are formed by up-diffusion of multiple p-type buried layers from the bulk-substrate during epitaxy. For these devices, the values of Vth variance and mismatch are computed as a function of device dimensions. The results show that the multiple-halo devices, in general, offer significantly lower Vth variance and mismatch compared to the conventional single-halo devices whereas, the emerging epitaxial-channel multiple-halo MOSFETs offer the lowest Vth variability compared to the conventional devices at the same technology node. And, the value of the mismatch coefficient for the emerging technology is about 0.68 mV × μm compared to that of 1.33 and 1.07 mV × μm for the conventional single-halo and multiple-halo technologies, respectively. This study, clearly, demonstrates the benefit of the emerging epitaxial-channel buried-halo MOSFETs in significantly reducing the effect of statistical dopant fluctuations on Vth at the advanced planar CMOS technology nodes.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

AbstractThis paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal–oxide–semiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors propose a heterojunction doping less tunnel field-effect transistor with an asymmetric double gate (HJ ADG DLTFET). This device employs a low bandgap material at the source region, which increases the BTBT rate at the channel–source interface leading to enhanced drive current while maintaining low off-current. Consequently, an increment of one order for ION (∼1.5 × 10−5 A/µm) compared to the conventional ADG DLTFET has been provided by this device. Additionally, the comparative analysis of the proposed device and conventional one has been performed to reveal the advantages of the proposed structure in terms of transfer characteristics, transconductance, gate-to-drain capacitance, cut-off frequency, gain–bandwidth product, device efficiency, and transconductance frequency product. Moreover, the effect of gate length and drain voltage variations has been analysed for HJ ADG DLTFET concerning the aforementioned characteristics.

Novel Hybrid Silicon SETMOS Design for Power Efficient Room Temperature Operation

A novel hybrid silicon Single Electron Transistor Metal Oxide Semiconductor (SETMOS) logic is evaluated for its functionality and usability. Emphasis is given on obtaining functionality at ambient temperature with low power consumption and significant drive. Performance is evaluated with respect to 22 nm Complementary Metal Oxide Semiconductor (CMOS) technology and other popular hybrid SETMOS topologies. The results produced here not only comprehend performance of various SET-CMOS based logic architectures, but they are also closer to real values as they consider effect of parasitic in respective topologies. Proposed work is power efficient, scalable, accurate and process compatible logic design, which uses less hardware and operates at room temperature. It relies on CMOS compatible fabrication of Silicon SET and P-Type Metal Oxide Semiconductor (PMOS) on same chip footprint. When compared with contemporary SETMOS hybrid circuits, it offers 90.29 % power improvement at the cost of 16.53 % reduction in speed.

Compact on‐chip millimetre wave bandpass filters with meandered grounding resonator in 0.13‐μm (Bi)‐CMOS technology

In this study, an ultra-compact meandered grounding resonator is proposed to design two millimetre wave bandpass filters (BPFs) in a standard 0.13-µm silicon-germanium (Bi)-complementary metal oxide semiconductor (CMOS) technology. The fundamental second-order prototype, namely BPF-I, consists of a pair of proposed resonators and a pair of grounded metal-insulator-metal (MIM) capacitors. To better understand the principle of the second-order BPF-I, an equivalent LC-circuit model and theoretical analysis method are presented in this study. Based on BPF-I, the second-order BPF-II is proposed by adding the additional two pairs of MIM capacitors to improve the frequency selectivity, by means of introducing a transmission zero at lower stopband. Finally, both of the two second-order BPFs are fabricated. The measured results show a good agreement with the full-wave simulation results. The insertion loss of the first BPF-I is 1.79 dB at the centre frequency of 46.6 GHz, and the fractional bandwidth is up to 96.5%. The second BPF-II has a centre frequency at 46.8 GHz with a fractional bandwidth of 94.1%. The minimum insertion loss is 2.08 dB and the lower stopband attenuation is up to 42.7 dB. Moreover, the die sizes of the two compact BPFs, excluding the test pads, are only 0.0197 mm2 (0.104 × 0.190 mm2).

Self-Mixing Model of Terahertz Rectification in a Metal Oxide Semiconductor Capacitance

Metal oxide semiconductor (MOS) capacitance within field effect transistors are of great interest in terahertz (THz) imaging, as they permit high-sensitivity, high-resolution detection of chemical species and images using integrated circuit technology. High-frequency detection based on MOS technology has long been justified using a mechanism described by the plasma wave detection theory. The present study introduces a new interpretation of this effect based on the self-mixing process that occurs in the field effect depletion region, rather than that within the channel of the transistor. The proposed model formulates the THz modulation mechanisms of the charge in the potential barrier below the oxide based on the hydrodynamic semiconductor equations solved for the small-signal approximation. This approach explains the occurrence of the self-mixing process, the detection capability of the structure and, in particular, its frequency dependence. The dependence of the rectified voltage on the bias gate voltage, substrate doping, and frequency is derived, offering a new explanation for several previous experimental results. Harmonic balance simulations are presented and compared with the model results, fully validating the model’s implementation. Thus, the proposed model substantially improves the current understanding of THz rectification in semiconductors and provides new tools for the design of detectors.

Spectrum detection based on compressive sensing inside multimode fibers

With the rapid development of integrated photonics, expensive and bulky commercial spectrometers force people to make more efforts to investigate high-performance, integrated and low-cost spectrometers. Spectrometers benefiting from the complementary metal-oxide semiconductor (CMOS) technology have greatly enriched the applications of spectrum detection while devices based on optical fibers still have potential development room. Owing to the strong dependence of multimode interference on wavelength generated in a multimode fiber, probe signals of arbitrary spectra could be detected by a detector array integrated on the top and reconstructed by using a compressive sensing (CS) algorithm. The CS algorithm has been widely used in signal processing, which saves more computing storage and time but maintains the same precision. With the interference pattern system, our spectrometer based on a fiber taper achieves a spectral resolution of 20 pm (one order of magnitude better than commercial spectrometers) and a detection bandwidth of more than 200 nm on a device length of 1 mm. After optimizing the energy function, the spectral reconstruction results show excellent detection capability and metamerism effect superior to RGB cameras or human eyes, providing a significant role for portable multi-functional on-chip systems in future.

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.