Abstract
This paper presents a comparative study on the effect of statistical dopant fluctuations on threshold voltage (Vth) of emerging and conventional metal-oxide-semiconductor (MOS) field-effect (FET) transistors (MOSFETs). In this context, three n-channel MOSFET structures representing three different complementary MOS (CMOS) technologies at the 20 nm node are considered. The structures represent a conventional device with symmetric halo or pocket regions around the n+source-drain formed by a single p-type dopant implantation; a second conventional device with symmetric p-type halo regions around the n+source-drain formed by multiple p-type dopant implantations; and an emerging epitaxial-channel device with symmetric p-type halo regions around the n+source-drain where the halo regions are formed by up-diffusion of multiple p-type buried layers from the bulk-substrate during epitaxy. For these devices, the values of Vth variance and mismatch are computed as a function of device dimensions. The results show that the multiple-halo devices, in general, offer significantly lower Vth variance and mismatch compared to the conventional single-halo devices whereas, the emerging epitaxial-channel multiple-halo MOSFETs offer the lowest Vth variability compared to the conventional devices at the same technology node. And, the value of the mismatch coefficient for the emerging technology is about 0.68 mV × μm compared to that of 1.33 and 1.07 mV × μm for the conventional single-halo and multiple-halo technologies, respectively. This study, clearly, demonstrates the benefit of the emerging epitaxial-channel buried-halo MOSFETs in significantly reducing the effect of statistical dopant fluctuations on Vth at the advanced planar CMOS technology nodes.
Highlights
IIN global race to scale down metal-oxide-semiconductor (MOS) field-effect transistors (FETs) [1]–[5], process variability in scaled complementary MOS (CMOS) technologies became a critical issue to control the variability in the performance of very large scale integrated (VLSI) devices, circuits, and systems [4], [6], [7]
Statistical analysis is used to model the effect of SDFs on Vth of MOSFETs and calculate Vth-variance, SDFs causing Vth-variance (sVth) between identical transistors in an IC chip and mismatch, s(∆Vth) between closely spaced identical paired-transistors within a die in an IC chip of a CMOS technology [11], [[24] as describe in the following subsections III A and III B, respectively
An exhaustive search on Vth mismatch reported a minimum value of Avt ≅ 2.0 mV × μm for silicon dioxide (SiO2) gate dielectric and polysilicon gate MOSFETs of advanced conventional CMOS technology at the nanometer node [7]
Summary
IIN global race to scale down metal-oxide-semiconductor (MOS) field-effect transistors (FETs) [1]–[5], process variability in scaled complementary MOS (CMOS) technologies became a critical issue to control the variability in the performance of very large scale integrated (VLSI) devices, circuits, and systems [4], [6], [7]. The variability in the performance of IC chips of a CMOS technology can be modeled by threshold voltage (Vth) variation in individual MOSFETs induced by statistical dopant fluctuations (SDFs) arising from discreteness of implanted dopants in the active region of the devices [9], [13], [14]. Due to this discreteness of dopants, probability exists for a random discrete dopant to occupy any random location in the channel region of a MOSFET causing Vth variability between identical devices in an IC chip. The advantage of the emerging epitaxial-channel MOSFETs in minimizing SDFs-induced Vth variability and mismatch compared to the conventional devices at the comparable CMOS technology node is discussed
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