Metal Oxide Semiconductor Field Effect Research Articles

TCAD-based investigation of 1/f noise in advanced 22 nm FDSOI MOSFETs

In this work, the mechanistic insights behind low-frequency noise (LFN) of the advanced ultrathin body and buried oxide fully depleted silicon-on-insulator based metal–oxide–semiconductor field effect transistor (MOSFET) are unveiled. The gate voltage-induced noise power spectral density (SVG) is inversely proportional to frequency f (i.e., SVG∝1/fγ, γ∼ 1 is the frequency exponent) for nMOSFET and pMOSFET. Detailed numerical simulations are performed and well calibrated to reported SVG vs f characteristics. Simulation results are consistent with the reported experimental observations. We demonstrate that LFN is caused by the charge carrier number fluctuation mechanism, which is originated by trapping and de-trapping of channel charge carriers via. bulk traps (from oxygen vacancies) in the hafnium dioxide (HfO2) layer, but not through traps at the silicon dioxide (SiO2)/channel interface. This work therefore explains the similar magnitude of SVG in both nMOSFET and pMOSFET observed experimentally and further suggests that oxygen vacancies inside gate oxides are critical to suppress the low-frequency noise in emerging high-k based MOSFETs.

Tunneling Current Calculation Using the Linear‐Bound Potential Model

A model of the tunneling current through an ultrathin insulating barrier coming from carriers in an inversion layer using a simple linear potential model is presented. This model provides analytical expressions for the wavefunctions of these carriers and simple equations to obtain numerically their corresponding eigenvalues. These expressions can be inserted in the tunneling current equation allowing a more simple understanding of the physics involved in this tunneling problem. As an example, one can fit the experimental results for the leakage current obtained by different authors in planar metal oxide semiconductor field effect transistors and also in a LaAlO3/SrTiO3 and a HfO2/Ge bilayer. The modification of the tunneling current when the dielectric constant is increased, a subject of interest in device applications, is explored.

Development of an inductive energy storage pulsed power supply using SiC semiconductor devices for ozone production by streamer discharges

An inductive energy storage (IES) pulsed power generator driven by a silicon carbide metal oxide semiconductor field effect transistor (SiC-MOSFET) with a blocking voltage of 1.2 kV was developed. The IES pulsed power generator consists of a capacitor, a pulsed transformer and the SiC-MOSFET used as an opening switch. The influence of the turn ratio of the pulsed transformer on the output voltage was evaluated. The output voltage amplitude increased with increasing secondary turn ratio. Under the conditions of no load, a peak output voltage of 13 kV and a pulse width of 120 ns were obtained with a voltage across the drain–source terminals of the MOSFET of 1 kV. The peak voltage increased, and the peak current and pulse width decreased, with increasing load resistance and decreased capacitance. The maximum energy transfer efficiency was obtained at 500 Ω and was approximately 56%.

Optimization of Impact Ionization in Metal–Oxide–Semiconductor Field-Effect Transistors for Improvement of Breakdown Voltage and Specific On-Resistance

For the past few decades, metal–oxide–semiconductor field-effect transistors (MOSFETs) have been the most important application in IC circuits. In certain circuit applications, the breakdown voltage and specific on-resistance serve as key electrical parameters. This article introduces a readily accessible approach to enhance the source–drain breakdown voltage (BVDS) of MOSFETs based on the Bipolar-CMOS-DMOS (BCD) platform without extra costs. By attentively refining the process steps and intricacies of the doping procedures, the breakdown voltages of NMOS and PMOS experienced increments of 3.4 V and 4.6 V, translating to enhancements of 31.5% and 50.3%. Parallel simulations offer insightful mechanistic explanations through simulation tools, facilitating superior outcomes. This initiative lays significant groundwork for the advancement of a comprehensive BCD process development framework.

Demonstration of aluminum nitride metal oxide semiconductor field effect transistor on sapphire substrate

Abstract Aluminum nitride (AlN) is a promising ultrawide bandgap material with significant advantages for power electronics and optoelectronic applications due to its high breakdown voltage, mobility, and thermal conductivity. AlN Schottky barrier diodes (SBDs) and metal semiconductor field effect transistors (MESFETs) have shown potential but are limited by issues such as high off-state leakage current and complex structures to achieve ohmic contacts. To address these challenges, we report on the fabrication and characterization of an AlN metal oxide semiconductor field effect transistor (MOSFET) with a recessed gate structure. The source and drain contacts were fabricated on n-doped AlN epitaxy using Ti-based contacts with a Ti/Al/Ti/Au metal stack. To evaluate the performance of these contacts, a circular transmission line model (CTLM) was employed, and contacts were annealed at various temperatures ranging from 750 to 950 °C in a nitrogen ambient. Our results reveal that unannealed Ti-based contacts on AlN showed no current conduction. However, annealing these contacts at 950 °C for 30 s significantly reduced the specific contact resistance to 0.148 Ω·cm2, achieving an ~80% reduction compared to samples annealed at 750 °C. Utilizing these optimized contact conditions, we fabricated, to the best of our knowledge, the first AlN MOSFET. The fabricated AlN MOSFET exhibits a threshold voltage of −10.91 V, an effective mobility of 2.95 cm2/Vs, an on-off current ratio spanning two orders of magnitude, and a reverse breakdown voltage of approximately ~250 V in air without a field plate. 

Asymmetric trench SiC MOSFET with integrated channel accumulation diode for enhanced reverse conduction and switching characteristics

A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 μC/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1 % reduction in reverse recovery charge and a 63.4 % decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4 % reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1 %.

Taguchi Method Statistical Analysis on Characterization and Optimization of 18-nm Double Gate MOSFETs

A bi-layer graphene with a multigate structure was intensified and analysed on an 18-nm Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) device to obtain an optimal performance parameter. The device has a gate structure made of Titanium Dioxide (TiO2) that serves as a high-k material and a metal gate made of Tungsten Silicide (WSix). The Silvaco TCAD Software which are ATHENA and ATLAS modules were used to enhance the fabrication process of virtual devices and to verify the electrical properties of a specific device. According to the International Technology Roadmap Semiconductor (ITRS) specifications of 0.179 V ± 12.7% for threshold voltage (VTH) and 20 nA/m for leakage current (ILEAK), the Taguchi L9 orthogonal array strategy was used to improve the device process parameters for optimum VTH and ILEAK. For the NMOS device, the process parameter of VTH Adjust Implant Dose was used as the dominant factor while Source/Drain (S/D) Implant Energy was used as the adjustment factor whereby for PMOS device, S/D Implant Energy was the dominant factor while S/D Implant Tilt was the adjustment factor in order to achieve a robust design through the Taguchi method implementation. The percentage affecting the process parameter is then applied to the results of the signal to noise ratio (SNR) of Nominal-the-best (NTB) for VTH and Smaller-the-better (STB) for ILEAK.

Pseudo-source gated beta-gallium oxide MOSFET

This study demonstrates pseudo-source-gated beta-gallium oxide (β-Ga2O3) metal oxide semiconductor field effect transistors (MOSFETs). The proposed pseudo-source gated transistor (pseudo-SGT) architecture has a thin (∼11 nm) recessed channel design, effectively emulating conventional SGT characteristics without significantly compromising on-current. The fabricated devices exhibit remarkable intrinsic gain of 104, low output conductance of 10−8 S/mm, transconductance of 10−3 S/mm, and drain saturation voltage of ∼1.5 V, while maintaining a drain current of 1.3 mA/mm. These enhanced performance metrics significantly expand the potential of β-Ga2O3 MOSFETs for the development of Ga2O3 monolithic power integrated circuits.

Selective-Area Growth of Hexagonal-to-Cubic GaN as an n-Type Metal–Oxide–Semiconductor Field-Effect Transistor Drain on a Nanogrooved Si(100) Substrate

Selective-Area Growth of Hexagonal-to-Cubic GaN as an n-Type Metal–Oxide–Semiconductor Field-Effect Transistor Drain on a Nanogrooved Si(100) Substrate

A Voltage Equalization Strategy for Series-Connected SiC MOSFET Applications

A novel clamped voltage equalization strategy is presented for series-connected Silicon Carbide (SiC) Metal–Oxide semiconductor Field-Effect transistors (MOSFETs) in this paper. Differences in device parameters and circuit asymmetry result in the uneven voltage distribution of series-connected SiC MOSFETs, which threatens the safe operation of the circuit. Dynamic voltage equalization is difficult to achieve due to the fast switching speed of SiC MOSFETs. This paper analyzes the switching characteristics and dynamic voltage equalization characteristics of SiC MOSFETs. Based on the analysis, an energy recovery strategy based on the clamping auxiliary circuit is proposed. A 2.8 kW (50 KHz) prototype is fabricated and tested to verify the strategy. Measurement results show that the maximum voltage stress is suppressed from 600 V to less than 320 V in the experimental condition.

A multi-source data fusion driven power field effect transistor health state assessment and remaining useful life prediction method

Abstract The metal oxide semiconductor field effect transistor (MOSFET) is subjected to various stresses due to the external and internal operating environments, leading to ageing and failure of the device. With multiple degradation mechanisms, a single piece of information can no longer fully reflect the health state of MOSFETs, so how to use multi-source data to characterise the state of the device and predict the remaining useful life (RUL) is an issue worth exploring. To address this problem, a method for constructing health indicators (HI) as well as predicting RUL using multi-source data is proposed. In this method, firstly, the features are computed by selecting the appropriate ageing signal from the ageing mechanism. Secondly, the extracted features are filtered using Pearson’s algorithm to find the features that are strongly correlated with longevity. Then, the filtered features are merged by dimensionality reduction using the kernel principal component analysis algorithm and the HI is constructed from the reduced result. Finally, an unsupervised clustering algorithm is used to classify the states based on the data distribution in HI, and the filtered features are used as input to the grey wolf optimisation bidirectional long short-term memory neural network to predict the RUL of the device. In this paper, the proposed method is validated using data from the MOSFET Accelerated Aging Experiment at the NASA Ames Centre of Excellence for Prediction. The results show that the method is able to achieve good results in health state assessment and RUL prediction of MOSFETs. The proposed method is an effective and comprehensive strategy that is more helpful for the operation and maintenance of electronics.

Analysis of Channel Current Noise in Small Nanoscale Metal Oxide Semiconductor Field Effect Transistors.

The shrinkage of metal oxide semiconductor field effect transistor (MOSFET) to the small size of the nanoscale results in changes in their channel current noise composition. This paper determines the channel current noise composition of 90nm MOSFET through experiments, and according to the device material and noise characteristics analysis, the channel current noise of 90nm and below is obtained, which not only contains thermal noise and suppressed channel shot noise, but also adds suppressed gate tunneling shot noise and cross-correlation noise. Then, Monte Carlo simulation of 10nm MOSFET noise is further used to determine the channel current composition of small size nanoscale devices. Subsequently, based on the device structure and fundamental characteristics of channel current noise, the channel current noise model is established. Finally, this model is employed to analyze the relationship between thermal noise, suppressed shot noise, cross-correlation noise, and channel current noise in relation to bias parameters and device characteristics. The theoretical results are basically consistent with the experimental and the simulated results, and the channel noise increases with the increase of bias voltage. This achievement holds promise for enhancing the operational efficiency, reliability, and lifetime of nanoscale small-sized MOSFET devices.

Pathfinding Process Development for the Realization of Atomic Precision Advanced Manufacturing (APAM)-Based Vertical Tunneling Field Effect Transistors for Enhanced Energy Efficiency

Since the end of Dennard scaling, where metal oxide semiconductor field effect transistor (MOSFET) operating frequency and energy efficiency improved with shrinking device dimensions [1], increasing transistor density is predicted to increase the total power consumption of a system [2]. A key limitation for MOSFETs is that the minimum rate of turn-on, or subthreshold swing (SS), is ~60 mV/decade at room temperature because of the Boltzmann statistics that dictate charge density. Thus, maintaining constant electric field without increasing energy consumption (i.e. gate bias) requires decreasing the SS by investigating alternative materials or device designs, like tunnel FETs (TFETs) [3]. Recent advances in atomic-scale control promise to provide control over quantum mechanical degrees of freedom which have hindered TFET performance in practice. These considerations make atomic precision advanced manufacturing (APAM) an appealing platform to realize a proof-of-concept TFET with atomic scale features [4,5].APAM can produce a 2D sheet of dopants in silicon beyond the solid solubility limit that can be patterned in-plane and capped with epitaxial silicon for strong carrier confinement in the out-of-plane direction (Figure 1). Indeed, improvements to planar TFETs that effectively have 1D channels with low on:off current ratios have been proposed by changing to a vertical geometry that leverages the carrier confinement afforded by 2D materials to create a 2D channel [6], though these materials are not typical in a silicon foundry. In contrast, APAM provides this carrier confinement while exclusively using materials and chemicals that are used in silicon foundries and with compatible processes [7]. In the APAM TFET (Figure 1.8.), a gate bias induces a layer of holes at the oxide/silicon interface that extends from the source, enabling tunneling between the 2D phosphorus-doped layer that comprise the drain and the 2D induced hole layer.As tunnelling occurs vertically through the epitaxial silicon cap, it becomes critical to determine the optimal growth temperature, to keep the dopants in a 2D sheet at low temperatures versus producing low-defect silicon at higher temperatures. Similarly, for optimal electric field control, it becomes critical to determine the optimal processing temperature to maintain the 2D dopant sheet and produce a low-defect gate oxide. The electronic thickness of the dopant layer can be measured using weak localization and the segregation of dopants out of the 2D sheet can be measured using secondary ion mass spectrometry. Our intial attemps at evaluating the electrical quality of the epitaxial silicon cap used PMOS transistors made with an ALD gate dielectric on APAM material without the buried phosphorus layer. Intuitively, we expect material grown at a higher temperature to produce a lower density of defects and therefore more performant PMOS, but find instead that the initial results demonstrate no systematic trend. These results potentially indicate there is an unknown variable obscuring the intentionally changed variable of growth temperature. Here, we propose several possible causes for this observation – both the variability from APAM processing or low-temperature microfabrication could mask an underlying trend.In summary, an APAM TFET provides a path toward increasing energy efficiency of transistors by decreasing SS compared to MOSFETs. The process tradeoffs that produce tightly confined 2D doped layers compared to low defect materials are starting to be explored using PMOS devices. Here, we report on the impact of process variability in drawing conclusions from these devices toward the realization of an APAM TFET.SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.[1] R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE J. Solid-State Circuits 9, 256 (1974).[2] https://irds.ieee.org/[3] J. Koga et al., “Negative differential conductance in three‐terminal silicon tunneling device”, Applied Physics Letters, 69, 1435 (1996).[4] T.-M. Lu et al., “Path towards a vertical TFET enabled by atomic precision advanced manufacturing”, 2021 Silicon Nanoelectronics Workshop (2021).[5] X. Gao et al., “Modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor”, 2021 SISPAD, 102 (2021).[6] H. Lu et al., “Tunnel Field-Effect Transistors: State-of-the-Art”, IEEE J. Electron Device Society, 2, 44 (2014).[7] S. Misra et al., “Method of chemical doping that uses CMOS-compatible processes”, U.S. Patent 11,798,808. Figure 1

High-Quality 4H-SiC Homogeneous Epitaxy via Homemade Horizontal Hot-Wall Reactor

In this paper, using a self-developed silicon carbide epitaxial reactor, we obtained high-quality 6-inch epitaxial wafers with doping concentration uniformity less than 2%, thickness uniformity less than 1% and roughness less than 0.2 nm on domestic substrates, which meets the application requirements of high-quality Schottky Barrier Diode (SBD) and Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) devices. We found that increasing the carrier gas flow rate can minimize source gas depletion and optimize the doping uniformity of the 6-inch epitaxial wafer from over 5% to less than 2%. Moreover, reducing the C/Si ratio significantly can suppress the “two-dimensional nucleation growth mode” and improve the wafer surface roughness Ra from 1.82 nm to 0.16 nm.

An investigation of 60Co gamma radiation induced damage in N-channel MOSFETS at cryogenic temperature.

N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 60Co gamma radiation in the dose range of 100 krad to 6Mrad at cryogenic (77K) and room temperatures (300K). The MOS devices irradiated at 77K and 300K were characterized at 77K and 300K respectively. The different electrical parameters of MOSFET such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot) and mobility of the charge carriers (μ) were studied as a function of total dose. A considerable increase in ΔNit and ΔNot and decrease in Vth was observed after irradiation. The 77K irradiation results were then compared with 300K irradiation results and found that the degradation in the electrical characteristics is more for the devices irradiated at 300K.

Photon-assisted electron depopulation of 4H-SiC/SiO2 interface states in n-channel 4H-SiC metal–oxide–semiconductor field effect transistors

4H-SiC/SiO2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/SiO2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/SiO2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/SiO2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes.

Multi-objective topology optimization design of silicon carbide metal oxide semiconductor field effect transistors power module liquid-cooled heatsink for electric vehicles

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) is gradually replacing silicon-based insulated gate bipolar transistor (IGBT) as the switching devices in electric vehicle power inverters due to its higher operating temperatures, switching speeds, and frequencyies. However, the high switching frequency of SiC MOSFETs can increase the losses of the power inverter, resulting in an increase in the temperature, which will limit the performance of power inverters. The improvement of power module performance is mainly controlled by optimizing its control methods during operation and improving its cooling system. Currently, the liquid-cooled heatsink used in power modules have disadvantages such as large flow resistance and poor heat dissipation performance. In order to enhance the performance of the heatsink, this study first established a three-dimensional finite element model of SiC MOSFETs power module based on a pin fin heatsink. The accuracy of the model was verified by numerical and experimental methods. Secondly, based on numerical analysis, a multi-objective topology optimization method for the power module liquid-cooled heatsink is proposed. This method takes heat exchange and fluid dissipation energy as the objective function and uses weight factors to adjust the influence of each on the objective functions. Additionally, the temperature distribution of the heatsink is considered to optimize its performance. Finally, the numerical results show that the topology-optimized heatsink exhibits better performance at high coolant volumetric flow rates. When the coolant volumetric flow rate is 14 L/min, the pressure drops of topology-optimized heatsink is reduced by 63.94 % and the junction temperature of the power module is reduced by 0.24 % compared with the pin fin heatsink. This topologically optimized heatsink could be helpful to improve the performance of existing power module heatsinks.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

High-Performance Sub-10 nm Two-Dimensional SbSeBr Transistors through Transport Orientation.

Exploring two-dimensional (2D) materials with a small carrier effective mass and suitable band gap is crucial for the design of metal oxide semiconductor field effect transistors (MOSFETs). Here, the quantum transport properties of stable 2D SbSeBr are simulated on the basis of first-principles calculations. Monolayer SbSeBr proves to be a competitive channel material, offering a suitable band gap of 1.18 eV and a small electron effective mass (me*) of 0.22m0. The 2D SbSeBr field effect transistor (FET) with 8 nm channel length exhibits a high on-state current of 1869 μA/μm, low power consumption of 0.080 fJ/μm, and small delay time of 0.062 ps, which can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices. Moreover, despite the monolayer SbSeBr having an isotropic me*, the asymmetrical band trends enable SbSeBr FETs to display transport orientation, which emphasizes the importance of band trends and provides valuable insights for selecting channel materials.