Pathfinding Process Development for the Realization of Atomic Precision Advanced Manufacturing (APAM)-Based Vertical Tunneling Field Effect Transistors for Enhanced Energy Efficiency

Abstract

Since the end of Dennard scaling, where metal oxide semiconductor field effect transistor (MOSFET) operating frequency and energy efficiency improved with shrinking device dimensions [1], increasing transistor density is predicted to increase the total power consumption of a system [2]. A key limitation for MOSFETs is that the minimum rate of turn-on, or subthreshold swing (SS), is ~60 mV/decade at room temperature because of the Boltzmann statistics that dictate charge density. Thus, maintaining constant electric field without increasing energy consumption (i.e. gate bias) requires decreasing the SS by investigating alternative materials or device designs, like tunnel FETs (TFETs) [3]. Recent advances in atomic-scale control promise to provide control over quantum mechanical degrees of freedom which have hindered TFET performance in practice. These considerations make atomic precision advanced manufacturing (APAM) an appealing platform to realize a proof-of-concept TFET with atomic scale features [4,5].APAM can produce a 2D sheet of dopants in silicon beyond the solid solubility limit that can be patterned in-plane and capped with epitaxial silicon for strong carrier confinement in the out-of-plane direction (Figure 1). Indeed, improvements to planar TFETs that effectively have 1D channels with low on:off current ratios have been proposed by changing to a vertical geometry that leverages the carrier confinement afforded by 2D materials to create a 2D channel [6], though these materials are not typical in a silicon foundry. In contrast, APAM provides this carrier confinement while exclusively using materials and chemicals that are used in silicon foundries and with compatible processes [7]. In the APAM TFET (Figure 1.8.), a gate bias induces a layer of holes at the oxide/silicon interface that extends from the source, enabling tunneling between the 2D phosphorus-doped layer that comprise the drain and the 2D induced hole layer.As tunnelling occurs vertically through the epitaxial silicon cap, it becomes critical to determine the optimal growth temperature, to keep the dopants in a 2D sheet at low temperatures versus producing low-defect silicon at higher temperatures. Similarly, for optimal electric field control, it becomes critical to determine the optimal processing temperature to maintain the 2D dopant sheet and produce a low-defect gate oxide. The electronic thickness of the dopant layer can be measured using weak localization and the segregation of dopants out of the 2D sheet can be measured using secondary ion mass spectrometry. Our intial attemps at evaluating the electrical quality of the epitaxial silicon cap used PMOS transistors made with an ALD gate dielectric on APAM material without the buried phosphorus layer. Intuitively, we expect material grown at a higher temperature to produce a lower density of defects and therefore more performant PMOS, but find instead that the initial results demonstrate no systematic trend. These results potentially indicate there is an unknown variable obscuring the intentionally changed variable of growth temperature. Here, we propose several possible causes for this observation – both the variability from APAM processing or low-temperature microfabrication could mask an underlying trend.In summary, an APAM TFET provides a path toward increasing energy efficiency of transistors by decreasing SS compared to MOSFETs. The process tradeoffs that produce tightly confined 2D doped layers compared to low defect materials are starting to be explored using PMOS devices. Here, we report on the impact of process variability in drawing conclusions from these devices toward the realization of an APAM TFET.SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.[1] R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE J. Solid-State Circuits 9, 256 (1974).[2] https://irds.ieee.org/[3] J. Koga et al., “Negative differential conductance in three‐terminal silicon tunneling device”, Applied Physics Letters, 69, 1435 (1996).[4] T.-M. Lu et al., “Path towards a vertical TFET enabled by atomic precision advanced manufacturing”, 2021 Silicon Nanoelectronics Workshop (2021).[5] X. Gao et al., “Modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor”, 2021 SISPAD, 102 (2021).[6] H. Lu et al., “Tunnel Field-Effect Transistors: State-of-the-Art”, IEEE J. Electron Device Society, 2, 44 (2014).[7] S. Misra et al., “Method of chemical doping that uses CMOS-compatible processes”, U.S. Patent 11,798,808. Figure 1