Metal-oxide-semiconductor Field-effect Transistors Research Articles

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Lowering of Schottky Barrier Height in a Vertical Pillar MOSFET by Deuterium Annealing

The Schottky barrier height (Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> ) is lowered by high-pressure deuterium annealing (HPDA), in a vertical pillar (VP) metal-oxide-semiconductor field effect transistor (MOSFET). Typical device characteristics were comparatively studied before and after HPDA. A change of contact resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) at a Schottky junction was also analyzed by using a transmission line method (TLM). Moreover, HPDA effects on the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> were characterized on different crystal orientations of silicon, which has a different number of traps. HPDA is more effective to lower the Φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> at (111) orientation than at (100) orientation because a greater number of interface traps can be passivated for an orientation with a high Miller index. Finally, a deuterium peak was physically profiled across the Schottky junction by use of time-of-flight secondary ion mass spectrometry (ToF-SIMS).

Design and implementation of a temperature-compensated corrector magnet power supply for the Taiwan Photon Source

The Taiwan Photon Source (TPS) is a widely recognised 3 GeV synchrotron light source. It has demonstrated exceptional performance in average beam downtime and meeting international standards over its successful ten-year operation. Regular equipment updates are conducted for all subsystems to ensure continuous improvement and maintain an optimal research facility environment. This study focuses on designing and implementing a temperature-compensated corrector magnet power supply for the TPS. The power supply incorporates a high-bandwidth, compact, cost-effective, bipolar, and highly precise shunt resistor as the current feedback component. A temperature control copper box and temperature compensation circuit are employed to improve the thermal equilibrium time of the output current. A laboratory-developed TPS-corrected magnet power supply with temperature compensation control has been successfully developed through these measures. The prototype exhibits a maximum output current of 10 A and operates at a voltage of 40 V. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are utilised as the power switch in a full-bridge (H-bridge) configuration with a driving frequency of 40 kHz. The output current ripple is effectively maintained at 100 μA for a 10 A output, and the stabilisation time is achieved within 5 minutes. The control loop design of the prototype has been verified to achieve fast and stable output current performance. The completed prototype demonstrated a -3 dB bandwidth of 2.57 kHz when tested with an input reference signal of 0.1 V. Finally, a hardware prototype circuit was constructed in the power supply laboratory, featuring an input voltage of 48 V, an output current of 10 A, and a maximum power capacity of 400 W.

Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures

The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

Design and Comparative Analysis of an Ultra-Highly Efficient, Compact Half-Bridge LLC Resonant GaN Converter for Low-Power Applications

For low-power applications, this paper presents the development and design of a compact and ultra-highly efficient half-bridge LLC resonant converter. By using Galium Nitride (GaN) devices and high-efficient magnetics, the efficiency and power density of resonant converters can be improved. Compared to Silicon MOSFETs, GaN high-electron-mobility transistors (GaN HEMT) have a lower output capacitance and gate charge, resulting in lower driving loss and shorter dead times. Consequently, the proposed LLC converter based on GaN devices has excellent performance characteristics such as ultra-high efficiency, low switching losses, compact size, high voltage endurance, high operating temperature and high operating frequency. Furthermore, the proposed resonant converter features soft switching properties that ensure that the switches and diodes on the primary side are always switched at zero voltage and current. By doing so, LLC resonant converter switching losses are significantly reduced by up to 3.1%, and an overall efficiency of 98.5% is achieved. The LLC resonant converter design with GaN HEMT has great advantages over Si MOSFET solution regarding efficiency, overall losses, switching loose and power factor correction. A 240 W, 240 V to 60 V half-bridge GaN HEMT LLC resonant converter is simulated with a switching frequency of 75 KHz, along with the comparative analysis of the Si metal oxide semiconductor field effect transistor (MOSFET) solution. Moreover, the design and analysis of highly efficient magnetics with a power factor of 0.99 at full load is presented. A 240-Watt single stage LED driver with power factor correction is also designed to verify and compare the performance of proposed LLC resonant converter.

β-Ga2O3 MOSFETs electrical characteristic study of various etching depths grown on sapphire substrate by MOCVD

β-Ga2O3 thin films with both a 45 nm Si-doped conductive epilayer and unintentionally doped epilayer were grown on c-plane sapphire substrate by metalorganic chemical vapor deposition. β-Ga2O3 based metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 20 nm and 40 nm (it indicated gate depth with 70 nm and 50 nm, respective), respectively, and without said recessing process. The conductivity of β-Ga2O3 epilayers was improved through low in situ doping using a tetraethoxysilane precursor to increase MOSFET forward current density. After recessing, MOSFET operation was transferred from depletion to enhanced mode. In this study, the maximum breakdown voltage of the recessed 40 nm transistor was 770 V. The etching depth of a recessed-gate device demonstrates its influence on device electrical performance.

A 600 W Photovoltaic Groundwater Pumping System Based on LLC Converter and Constant Voltage MPPT

The work consists of the development of a market-friendly 600 W photovoltaic battery-less water pumping system. The system is composed of four 280 Wp solar panels, an auxiliary 10 W solar panel, a three-phase converter and a ½ horsepower (hp) submersible water pump. The electronic stage involves a resonant DC-DC converter in series with a voltage source three-phase inverter. The novelties of this work are related to the use of a resonant DC-DC converter with fixed duty-cycle and frequency for water pumping application, the use of Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) for solving converter startup issues, and the use of a constant voltage maximum power tracking (MPPT) algorithm with auxiliary panels. The work displays the design of the converter, simulation and experimental results, discussions, and cost evaluation. The feasibility of the system is studied for the water requirements of a beef cattle farm in Brazil.

Temperature and total ionizing dose effects of SiC MOSFET and their synergistic characteristics

In light of the extreme environmental conditions of temperature and radiation faced by silicon carbide Metal–Oxide-Semiconductor Field-Effect Transistor (SiC MOSFETs) in aerospace electronic systems, the damage characteristics induced by high-temperature stress and Total Ionizing Dose (TID) radiation were compared. Moreover, the synergistic effect of temperature stress and TID on the performance of SiC MOSFETs was studied. The impact of temperature stress and radiation on threshold voltage and static power current is consistent; However, the degradation trend of on-resistance is opposite. The research shows that after temperature stress removal, the change in device performance parameters can be recovered. The total ionizing dose radiation can cause permanent damage to the device; In the environment of temperature stress and radiation, the increase of temperature can weaken or restrain part of radiation damage.

A non-defect precursor gate oxide breakdown model.

Understanding defect creation is central to efforts to comprehend gate dielectric breakdown in metal-oxide-semiconductor-field-effect-transistors (MOSFETs). While gate dielectrics other than SiO2 are now popular, models develop for SiO2 breakdown are used for these dielectrics too. Considering that the Si-O bond is very strong, modeling efforts have focused in ways to weaken it so that defect creation (bond-breaking) is commensurate with experimental observations. So far, bond-breaking models rely on defect-precursors to make the energetics manageable. Here it is argued that the success of the percolation model for gate oxide breakdown precludes the role of defect precursors in gate oxide breakdown. It is proposed that defect creation involves "normal" Si-O bonds. This new model relies on the fact that hole transport in SiO2 is in the form of a small polaron - meaning that it creates a transient local distortion as it travels. It is this transient distortion that enables normal Si-O bonds to be weakened (albeit transiently) enough that breaking the bonds at a rate commensurate with measurements becomes possible without the help of the externally applied field.

High temperature stability of H-diamond high frequency MOSFET with 300°C grown Al2O3 dielectric

The high frequency H-diamond metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on single diamond substrate using 300°C ALD grown Al2O3 as gate dielectric and passivation layer. The devices gate length, gate/drain spacing and dielectric thickness are 100 nm, 2 μm, and 10 nm, respectively. The direct-current and frequency characteristics were investigated. The device shows a maximum saturation drain current of −492.6 mA/mm and gm of 135.2 mS/mm. The device shows good high temperature working performance, and the maximum saturation drain current only has a little decreasing of 7.6%. at 200°C. In addition, the device exhibits a maximum cut-off frequency of 36.2 GHz and maximum oscillation frequency of 70.5 GHz. The transient drain current response measurement indicates that the drain current can follow the changing of gate voltage at the frequency of 1 MHz. These results indicate that the Al2O3 dielectric is suitable for using in high frequency or the high-speed switching devices.

Low-frequency noise in quasi-ballistic monolithic Al–Ge–Al nanowire field effect transistors

In this work, Al2O3-passivated, monolithic, and crystalline Al–Ge–Al heterostructure nanowire field effect transistors (FETs) with Ge channel lengths ranging from 18 to 826 nm are analyzed from a low-frequency noise perspective. 1/f and random telegraph noise (RTN) are analyzed in an accumulation mode, where the hole channel is formed by applying a back-gate potential VG. The normalized power spectral density of drain current fluctuations of 1/f noise (SID/ID2) at medium currents follows nearly an 1/ID trend. 1/f noise is analyzed within both the mobility and carrier number fluctuation models (MFM and CNFM), respectively. Taking the MFM into account, the Hooge noise parameter α spreads in the interval of 1.5 × 10−4 to 4 × 10−2, with lower values for shorter devices. Using the same data and the CNFM, the density of interface states Dit in the Al2O3/GexOy/Ge system was estimated using the transconductance extracted from the quasi-static transfer I/V characteristics. The extracted Dit values range from 5 × 109 to 3 × 1012 cm−2 eV−1. Contact noise has also been observed in some devices at high currents. RTN analyzed in time domain exhibits a relative RTN amplitude in the 0.3%–20% range. Capture and emission time constants as a function of VG exhibit a typical behavior for metal oxide semiconductor FETs. The extracted noise parameters are comparable with Ge and III–V nanodevices of top-down and bottom-up technologies.

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices.

Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator-metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 108.

Measurement and gate-voltage dependence of channel and series resistances in lateral depletion-mode β-Ga2O3 MOSFETs

Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified transfer length method (TLM) to obtain sheet resistances in the gated and ungated regions as well as to observe their gate electric field dependence. The modified TLM requires the contact resistance to be independent of the gate-source voltage, or changing current density. We verify this by performing measurements on conventional TLM structures in dark and UV conditions and observe a changing current density with constant contact resistance, enabling the development of the proposed method. The conventional and modified TLM give sheet resistances of 20.0 kΩ sq−1 ± 1.0 kΩ sq−1 and 27.5 kΩ sq−1 ± 0.8 kΩ sq−1, respectively. Using a traditional method for determining the channel resistance, the modified TLM improves the convergence of the channel resistances between the three devices, showing higher accuracy than the conventional TLM structures. Gate-source voltage dependence of the sheet resistances is seen in the ungated regions, leading to non-ideal behavior which cannot be observed using the traditional method and conventional TLM structures. These results and analysis methods are important in improving MOSFET parameter extraction and understanding the gate electric field effects on the channel and series resistances in β-Ga2O3 MOSFETs.

Study on the Deposition Characteristics of Molybdenum Thin Films Deposited by the Thermal Atomic Layer Deposition Method Using MoO2Cl2 as a Precursor

In this study, we conducted research on manufacturing molybdenum (Mo) thin films by a thermal atomic layer deposition method using solid MoO2Cl2 as a precursor. Mo thin films are widely used as gate electrodes and electrodes in metal-oxide semiconductor field-effect transistors. Tungsten (W) has primarily been used as a conventional gate electrode, but it suffers from reduced resistivity due to the residual fluorine component generated from the deposition process. Thus, herein, we developed a Mo thin film with low resistivity that can substitute W. The MoO2Cl2 precursor used to deposit the Mo thin film exists in a solid state. For solid precursors, the vapor pressure does not remain constant compared to that of liquid precursors, thereby making it difficult to set process conditions. Furthermore, the use of solid precursors at temperatures 600 °C and above has many limitations. Herein, H2 was used as the reactive gas for the deposition of Mo thin films, and the deposition temperature was increased to 650 °C, which was the maximum processing temperature of the aluminum nitride heater. Additionally, deposition rate, resistivity change, and surface morphology characteristics were compared. While resistivity decreased to 12.9 μΩ∙cm with the increase of deposition temperature from 600 °C to 650 °C, surface roughness (Rq) was increased to 0.560 nm with step coverage of 97%. X-ray diffraction analysis confirmed the crystallization change in the Mo thin film with increasing process temperature, and a certain thickness of the seed layer was required for nucleation on the initial wafer of the Mo thin film. Thus, the molybdenum nitride thin film was deposited after the 4 nm deposition of Mo thin film. This study confirmed that crystallinity of Mo thin films must be increased to reduce their resistivity and that a seed layer for initial nucleation is required.

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN.

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | - 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

SiC trench MOSFET with dual shield gate and optimized JFET layer for improved dynamic performance and safe operating area capability

A novel silicon carbide (SiC) trench metal–oxide–semiconductor field-effect transistor (MOSFET) with a dual shield gate (DSG) and optimized junction field-effect transistor (JFET) layer (ODSG-TMOS) is proposed. The combination of the DSG and optimized JFET layer not only significantly improves the device’s dynamic performance but also greatly enhances the safe operating area (SOA). Numerical analysis is carried out with Silvaco TCAD to study the performance of the proposed structure. Simulation results show that comparing with the conventional asymmetric trench MOSFET (Con-ATMOS), the specific on-resistance (R on,sp) is significantly reduced at almost the same avalanche breakdown voltage (BV av). Moreover, the DSG structure brings about much smaller reverse transfer capacitance (C rss) and input capacitance (C iss), which helps to reduce the gate–drain charge (Q gd) and gate charge (Q g). Therefore, the high frequency figure of merit (HFFOM) of R on,sp ⋅ Q gd and R on,sp ⋅ Q g for the proposed ODSG-TMOS are improved by 83.5% and 76.4%, respectively. The switching power loss of the proposed ODSG-TMOS is 77.0% lower than that of the Con-ATMOS. In addition, the SOA of the proposed device is also enhanced. The saturation drain current (I d,sat) at a gate voltage (V gs) of 15 V for the ODSG-TMOS is reduced by 17.2% owing to the JFET effect provided by the lower shield gate (SG) at a large drain voltage. With the reduced I d,sat, the short-circuit withstand time is improved by 87.5% compared with the Con-ATMOS. The large-current turn-off capability is also improved, which is important for the widely used inductive load applications.

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

Breakdown Characteristics of Ga2O3-on-SiC Metal-Oxide-Semiconductor Field-Effect Transistors

Ultra-wide bandgap semiconductor gallium oxide (Ga2O3) features a breakdown strength of 8 MV/cm and bulk mobility of up to 300 cm2V−1s−1, which is considered a promising candidate for next-generation power devices. However, its low thermal conductivity is reckoned to be a severe issue in the thermal management of high-power devices. The epitaxial integration of gallium oxide thin films on silicon carbide (SiC) substrates is a possible solution for tackling the cooling problems, yet premature breakdown at the Ga2O3/SiC interface would be introduced due to the relatively low breakdown strength of SiC (3.2 MV/cm). In this paper, the on-state properties as well as the breakdown characteristics of the Ga2O3-on-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated by using the technology computer-aided design (TCAD) approach. Compared with the full-Ga2O3 MOSFET, the lattice temperature of the Ga2O3-on-SiC MOSFET was decreased by nearly 100 °C thanks to the high thermal conductivity of SiC. However, a breakdown voltage degradation of &gt;40% was found in an unoptimized Ga2O3-on-SiC MOSFET. Furthermore, by optimizing the device structure, the breakdown voltage degradation of the Ga2O3-on-SiC MOSFET is significantly relieved. As a result, this work demonstrates the existence of premature breakdown in the Ga2O3-on-SiC MOSFET and provides feasible approaches to further enhance the performance of hetero-integrated Ga2O3 power devices.

650V Vertical SiC MOSFETs and Diodes with Improved Terrestrial-Neutron Single-Event Burnout

Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm2) such that essentially no failures (0.01 FIT/cm2) are expected at 400V drain-source bias (VDS) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given VDS operation condition, the FIT/cm2 can be decreased by 10 - 100 times, depending on the VDS value. This allows operation at about 75V higher VDS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

On the Frequency Dependence of the Gate Switching Instability in Silicon Carbide MOSFETs

Silicon carbide power metal-oxide semiconductor field-effect transistors (MOSFETs) are suitable for more compact and energy efficient electric power conversion, pushing forward numerous key technologies in emission-free mobility and green power generation. These applications require fast gate switching up to hundreds of kilohertz. Typically, to assure a clear turn-off state of the electron channel, a negative turn-off gate bias is used in conjunction with a positive turn-on gate bias. Recently, several reports have revealed a new and so far unknown degradation mechanism that emerges during such operation conditions in apparently all commercial silicon carbide MOSFETs. As this mechanism arises upon gate switching, the terms gate switching instability (GSI) and gate switching stress (GSS) for the mechanism and the associated stress, respectively, have been introduced.Here, we show that this degradation mechanism does not depend on the used frequency up to at least 2 MHz, but that it is actually related to the cumulative number of switching cycles. For this purpose, we performed measurements at various frequencies comprising ultra-fast in-situ measurements of the threshold voltage and pre- and post-stress characterization by impedance analysis. The results are important both for understanding the underlying physics and for developing a correct methodology for industrial device qualification.