Performance Of Metal-oxide-semiconductor Field-effect Transistors Research Articles

A Programmable Gate Driver Module-Based Multistage Voltage Regulation SiC MOSFET Switching Strategy

Silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), as a new material, have the advantages of low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency compared with silicon (Si)-based MOSFETs. Therefore, in many industrial applications, Si MOSFETs have been replaced by SiC MOSFETs. However, as the switching speed increases exponentially, some problems are amplified, the most serious of which is the overshoot of current and voltage. The increase in voltage and current slope caused by high switching speeds inevitably leads to overshoot, oscillations, and additional losses in the circuit. This paper focusses on the actual performance of the optimised switching strategy (OSS) in circuit testing and combines the existing simulation results to verify the practicability of OSS. In this paper, the optimised switching strategy is introduced first, and then, the LTspice model of SiC MOSFET is established in detail and verifies the feasibility of the OSS through half-bridge circuit simulation. Finally, the test platform is built using a programmable gate drive module (2ASC-12A1HP). Through a 400 V/30 A double-pulse test, the practicality of the OSS is verified. The experiments show that the OSS can greatly improve the switching performance of SiC MOSFETs.

High-Performance WS2 MOSFETs with Bilayer WS2 Contacts.

WS2 is a promising transition-metal dichalcogenide (TMDC) for use as a channel material in extreme-scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its monolayer thickness, high carrier mobility, and its potential for symmetric n-type and p-type MOSFET performance. However, the formation of stable, low-barrier-height contacts to monolayer TMDCs continues to be a challenge. This study introduces an innovative approach to realize high-performance WS2 MOSFETs by utilizing bilayer WS2 (2L-WS2) in the contact region grown through a two-step chemical vapor deposition process. The 2L-WS2 devices demonstrate a high I ON/I OFF ratio of 108 and a saturated drain current, I D(SAT), of 280 μA/μm (386 μA/μm) at room temperature (78 K), even while still using conventional metal (Pd or Ni) contacts. Devices featuring a 1L-WS2 channel and 2L-WS2 in the contact regions were also fabricated, and they exhibited performance comparable to that of 2L-WS2 devices. The devices also exhibit good stability with nearly identical performance after storage over a 13 month period. The study highlights the benefits of a hybrid channel thickness approach for TMDC transistors.

The synergistic effect of vertical structural parameters of vertical-type two-dimensional hole gas diamond MOSFETs on improving the overall performance of devices based on TCAD simulation

Vertical-type two-dimensional hole gas (2DHG) diamond metal-oxide-semiconductor field effect transistors (MOSFETs), featuring vertical geometry and typically p-channel, are poised for application in future logic technology, high-voltage and high-power miniaturization complementary circuits. P-channel achieving high breakdown voltage and low on-resistance can be realized through the use of p− drift layer, while a trench structure is shown to be beneficial for increasing the drain current density of vertical-type devices. However, the cumulative impact of these key parameters on the performance of vertical-type diamond MOSFETs remains unclear. In this paper, we explore the physical mechanism that how the key parameters design affects on off-state, breakdown and output characteristics has been simulated using Silvaco TCAD tools. We propose a vertical-type trench-gate 2DHG diamond MOSFET that is favorable for general integration applications and exhibits equivalent performance to the double-gate vertical structure without relying on a high concentration of nitrogen doped layer. This demonstrates that our work offers a universal approach for optimizing the comprehensive device performance in vertical-type structures, accounting for the effects of multiple parameters across all wide bandgap material-based FETs.

The heat dissipation by the multi-needle electrode structure ionic wind generator

Ionic wind generated by atmospheric pressure discharge can be used for propulsion, heat dissipation, food drying, which shows the unique advantages of no mechanical parts and fast response. However, the wind speed and the energy efficiency of ionic wind generator are very low, which limit its application. In this paper, an ionic wind generator, constructed with needle-net electrode structure and powered by high-voltage positive dielectric current (DC) power supply, is built for cooling of a metal oxide semiconductor field effect transistor (MOSFET). The energy efficiency and wind speed of the ionic wind generator are optimized by adjusting the electrode structure and applied voltage amplitude. The results show that when the discharge spacing is fixed at 10 mm and the optimal needle spacing is 17.5 mm with 6 needles at 14 kV, the ionic wind velocity can reach a maximum value 3.20 m s−1 and the energy efficiency is 1.90%. Under optimal experimental conditions, the heat dissipation performance of MOSFET is significantly enhanced compared to using only a heat sink. With cooling by the ionic wind generator, the MOSFET junction temperature can be lowered by about 29 °C after 240 s operation.

Non-equilibrium Green's function analysis of charge plasma-based source-drain electrode P-type MoTe2 MOSFET for high sensitivity hydrogen sensing

—The paper presents a novel P-type molybdenum ditelluride (MoTe2) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) designed for high sensitivity hydrogen sensing applications. Through the utilization of palladium at the source-drain charge plasma electrode, P+ regions at both ends are generated, obviating the necessity for low-dimensional MoTe2 doping. Simultaneously, the inclusion of palladium on both regions act as the sensing area, resulting in notably heightened sensitivity. The study employs Non-Equilibrium Green's Function (NEGF) formalism to investigate the carrier transport properties of the device. The results provide valuable insights into less explored area of p-type MOSFET performance as Hydrogen(H2) gas sensor and its potential.

The impact of gate length, oxide dielectric materials, and oxide thickness on the GaNNT MOSFETs performance.

The expansion of the integrated circuit industry in recent years has been primarily propelled by the progressive growth of metal-oxide-semiconductor field effect transistors (MOSFETs). The device is employed as a rapid switch in computers advanced. The switching speed of MOSFETs is significantly influenced by the selection of gate length, oxide dielectric materials, and oxide thickness. Gallium nitride nanotubes (GaNNT) with remarkable stability in ambient conditions, making them a promising candidate for use as channel material in the forthcoming era of MOSFET technology. This study utilizes ab initio simulation to examine the device functionality of double-gate (DG) GaNNT MOSFETs sub- under the impact of gate length, oxide dielectric material, and oxide thickness. The findings suggest that enhancing the gate length and dielectric constant, as well as reducing the oxide thickness, can lead to significant improvements in the ratio of , subthreshold swing (SS), transconductance ( ), power dissipation (PDP), and delay time ( ). The enhancement is notably conspicuous when considering a channel length that is for devices of n-type. Hence, GaNNT demonstrates significant potential as a channel material in the advancement of complementary MOSFETs that are compatible with both n-type and p-type devices.

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN.

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | - 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

Field Effect Transistor with Nanoporous Gold Electrode.

Nanoporous gold (NPG) has excellent catalytic activity and has been used in the recent literature on this issue as a sensor in various electrochemical and bioelectrochemical reactions. This paper reports on a new type of metal-oxide-semiconductor field-effect transistor (MOSFET) that utilizes NPG as a gate electrode. Both n-channel and p-channel MOSFETs with NPG gate electrodes have been fabricated. The MOSFETs can be used as sensors and the results of two experiments are reported: the detection of glucose and the detection of carbon monoxide. A detailed comparison of the performance of the new MOSFET to that of the older generation of MOSFETs fitted with zinc oxide gate electrodes is given.

Ballistic transport in 5.1 nm monolayer boron phosphide transistors for high-performance applications

Boron Phosphide is reported to be a semiconductor material with anisotropy, tunable bandgap, and high carrier mobility. We study the performance of 5.1 nm metal–oxide–semiconductor field-effect transistors (MOSFETs) based on boron phosphide using quantum transport simulation. The calculated results show that the on-state current can fulfill the requirements of the International Semiconductor Technology Roadmap (ITRS) for high-performance (HP) devices at the optimal doping concentration, but the gate control capability is not ideal. Furthermore, it is found that the gate control capability and on-state current can be significantly improved with the length being 1 nm by using the underlap (UL) structure. We also study the performance of boron phosphide MOSFET with different gate lengths (5–8 nm), and the results suggest that the shorter the gate length, the worse the gate control capability. Interestingly, the p-type boron phosphide MOSFET always outperforms the n-type MOSFET. This work will provide a new reference for the development of two-dimensional (2D) semiconductor devices.

(Invited) New Layout Styles to Boost the Electrical, Energy, and Frequency Response Performances of Analog MOSFETs, Considering a Wide Range of High Temperatures

The manuscript performs a review of the differentiated new layout styles for the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) that can boost their electrical performance and ionizing radiation tolerance. Firstly, we present the elements of the first generation of layout styles, the effects intrinsic to their structures, and the first-order analytical models of their drain current. After, we study the first element of the second generation of layout styles, which presents a hybrid gate geometry, aiming mainly to further reduce its effective channel length in comparison to those reached by the first generation and consequently further boosting the electrical performance of the analog MOSFETs. The experimental results in room temperature and high temperature found to show that the first element of the second generation can be considered an alternative hardness-by-design to improve the electrical performance and ionizing radiation of the analog MOSFETs.

The effect of gate geometric effect and polysilicon doping on the performance of scaled NMOS

Insufficiently high doping in polysilicon gates of metal oxide semiconductor field effect transistor (MOSFET) becomes unavoidable due to the demands for low-energy ion implantation and limited annealing conditions to achieve ultra-shallow source and drain junctions. This results in the poly-depletion effect for ultra-thin MOSFET, loss of current drive and shift in the threshold voltage. This problem gets intense when the device is further scaled down for the gate length and thickness of gate oxide. Hence, our current work focuses on the effect of gate geometrical effect and polysilicon gate doping on scaled n-channel MOSFET(NMOS) performance. The NMOS device was constructed using TCAD ATLAS tools from SILVACO software. Six different gate lengths of 0.6 μm, 0.4 μm, 0.2 μm, 60 nm, 40 nm and 20 nm were set, and the n-type doping concentration in the polysilicon gate was varied to 1× 1018, 1× 1020 and 1 × 1021 cm-3 respectively to see their effect on the NMOS I-V and C-V performances. The findings showed that as the gate length is scaled down, the drain current increases, and as the concentration of the polysilicon doping increases, the value of the threshold voltage, VTH decreases. Based on the simulation and data collected, it can be concluded that the optimum concentration of polysilicon doping that can reduce the poly-depletion effect is 1 × 1021 cm-3, and the optimum gate length that can be used to overcome the problem is 20 nm.

Electrode Engineering in MoS2 MOSFET: Different Semiconductor/Metal Interfaces

AbstractThe formation of Ohmic contact between metal electrode and 2D semiconductor channel is considered a key factor for performance improvement of 2D metal–oxide–semiconductor field‐effect transistors (MOSFET). However, the Schottky barrier at the metal electrode/2D semiconductor interfaces cannot be lowered effectively due to the pinning effect of Fermi levels, which makes it hard to obtain lower Ohmic contact resistance. Until now, although physical transfer metal electrode or inserted tunneling layer has been reported to get rid of the Fermi‐level pinning effect, these different designs of electrode engineering are not systematically compared. To serve better Ohmic contact, three different designs of electrode engineering are employed in 2D MoS2 MOSFET: evaporating Ag electrode on MoS2, transferring MoS2 to Ag electrode, and inserting ultrathin AlOx tunneling layer. Our experimental results demonstrate that the transferring MoS2 to Ag electrode in 2D MoS2 MOSFET can obtain the lowest contact resistance and Schottky barrier of 0.45 Ωcm and 12.8 meV, respectively. On this basis, photodiodes with obvious rectifying behavior are fabricated using schemes of electrode engineering, due to their different Schottky barrier high. The detailed contrastive analysis in our three different designs of electrode engineering can provide valuable guidance to optimize the performance of 2D semiconductor MOSFET.

Fabrication of inversion p-channel MOSFET with a nitrogen-doped diamond body

A normally-off inversion p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a nitrogen (N)-doped diamond body deposited using microwave plasma-enhanced chemical vapor deposition (MPECVD) was fabricated. The MOSFET exhibited a drain current density of −1.7 mA/mm. Thus far, this value is similar to the device performance of the inversion p-channel MOSFET fabricated using a phosphorus (P)-doped n-type diamond body. The N2 used for N-doping is safer than the PH3 used for P-doping; moreover, the doping concentration is highly controllable. Because the MOSFET, which is a classical electronic device, is driven by a gate voltage, smooth functioning was possible even at a deep donor level. The observed characteristics of the classic MOSFET operating via an N-doped body are crucial for the development of diamond power devices. In this paper, we discuss the significance of the N-doped diamond body and electrical characteristics of the inversion p-channel MOSFET fabricated using an N-doped diamond body.

LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges

This article presents, for the first time, a study about of behavior of the intrinsic effects from diamond layout style [longitudinal corner effect (LCE) and PArallel connection of MOSFETs with Different channel Lengths Effect (PAMDLE)] for metal–oxide–semiconductor field-effect transistors (MOSFETs) influenced by wide high-temperature ranges. These effects are capable of boosting the electrical performance of analog MOSFETs in relation to that of the standard MOSFET (rectangular gate shape). First, we have developed an experimental comparative study between MOSFETs implemented with the hexagonal layout style diamond MOSFET (DM) and its rectangular MOSFET (RM) counterpart, regarding that they present the same channel width and gate area, operating in a wide high-temperature range (from 300 to 573 K). These devices were manufactured with the technology of bulk complementary MOS (CMOS) integrated circuits (ICs) of 180 nm. The experimental results have shown that DM has obtained a better electrical performance of analog MOSFETs than the one observed in RM counterpart (for example, gains of 67% for saturation drain current and 90% for the transconductance), regardless of temperatures in which they were exposed. 3-D numerical simulations were used to justify the better electrical performance of DMs due to the LCE and PAMDLE effects, in relation to one of the RM counterparts, by observing the behavior of electrostatic potentials, longitudinal electric fields, and drain current densities of the devices as the temperature increases. Besides, a study about the short-channel effect has shown that DM can suppress this effect more effectively than RM at room temperature due to a smaller reduction in effective channel length of DM.

Impact of source doping profile on the performance of CNT TFETs and MOSFETs: design aspects for fabrication tolerance

In this work, the effect of the source doping profile due to possible fabrication aspects has been investigated and discussed for both carbon nanotube tunneling field effect transistors (TFETs) and metal oxide semiconductor field effect transistors (MOSFETs). A quantum 2D simulator, which is based on self-consistent solution of non-equilibrium Green’s function and Poisson’s equation, is utilized. It has been found that the source doping gradient remarkably affects the drain current, especially in the case of TFET. This raises the need for fabrication precautions and design to retain higher ON-state current. Besides, the high frequency behavior of TFET and MOSFET structures is inspected in terms of cut-off frequency f T. It is found that the source doping profile has a more significant impact on TFETs than on MOSFETs. For better performance, source doping needs to be abrupt. However, with a small source-gate underlapping, degradations due to gradual doping can be reduced. It is also found that a TFET with source/drain low-k oxide spacer can achieve more immunity to these degradations than the single oxide structure.

Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs

The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges

The analog/radiofrequency (RF) performance of a strained-silicon (s-Si) graded-channel dual-material double gate (GC-DMDG) metal–oxide–semiconductor field-effect transistor (MOSFET) with interface charges is investigated by using Sentaurus technology computer-aided design (TCAD) software. The analog/RF figures of merit of the proposed s-Si GC-DMDG MOSFET, including the intrinsic voltage gain, transconductance generation factor, early voltage, unity-current gain frequency ( $$f_{\rm t}$$ ), transconductance–frequency product (TFP), gain–frequency product (GFP), and gain–transconductance–frequency product (GTFP), are evaluated for different values of device parameters such as the strain in the silicon, the interface charge density, and the thicknesses of the oxide and substrate layers. The simulation results exhibit that the proposed s-Si GC-DMDG MOSFET device attains lower values of transconductance and output conductance and a higher value of early voltage compared with the s-Si graded-channel double-gate (GC-DG) MOSFET. Besides, the proposed s-Si GC-DMDG MOSFET device provides better performance in terms of $$f_{\rm t}$$ , TFP, GFP, and GTFP in comparison with the s-Si GC-DG MOSFET in the strong inversion region, and vice versa in the subthreshold region.

Heat transport properties of alumina gate insulator films on Ge substrates fabricated by atomic layer deposition

Amorphous Al2O3 films deposited by atomic layer deposition (ALD) on Ge substrates are a typical gate insulator dielectric used in Ge channel metal-oxide semiconductor field-effect transistor (MOSFET) devices. As Joule heating in the Ge channel alters the MOSFET performance, the thermal transport properties of ALD-Al2O3 films and interfaces between Al2O3 and Ge have become important characteristics. This study measures the thermal transport properties of Al2O3 films on Ge substrates using the thermo-reflectance method. The thermal conductivity кm of the Al2O3 films and the thermal resistivity of the Al2O3/Ge interface were estimated to be 0.83 W m−1 K−1 and 2.8 × 10−8 m2 K W−1, respectively. A significant reduction from the thermal conductivity of crystalline Al2O3 (46 W m−1 K−1) and the large thermal resistivity of the interface were observed. To understand the thermal transport mechanism in the ALD-Al2O3 film, thermal transport was simulated using phonon-based and diffuson theories. It was found that diffuson theory was better at explaining the relatively low thermal conductivity of ALD-Al2O3. The thermal resistivity of the Al2O3/Ge interface was discussed in comparison with that of SiO2/Si interface. The improved understanding of the thermal transport properties of the ALD-Al2O3/Ge stacking structures is essential to obtain the correct prediction of the electrical performance of the MOSFET devices.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.