Metal Oxide Semiconductor Field Effect Research Articles

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Background:The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.Objective:FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.Methods:An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).Results:The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.Conclusion:MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

Controlling Electron Mobility of Strongly Coupled Organic Semiconductors in Mirrorless Cavities

AbstractRecent experiments on the strong light‐matter coupling between an organic semiconductor and a plasmonic mode propose an unconventional way to enhance conductivity. Herein, it is shown that mirrorless cavities can boost conductivity by simply structuring the refractive indices of the multilayers in a commercially available metal oxide semiconductor field effect transistor (MOSFET). Perylene diimide (an organic semiconductor dye) molecules are deposited on a MOSFET device. The refractive index mismatch between the silicon/silicon dioxide/dye/air results in light confinement. The frequency of this confined light is tuned by changing the thickness of the organic semiconductor layer. Interestingly, an increase in electron mobility was observed once the electronic transition of the dye molecules and the second‐order cavity mode enter into the strong coupling regime. Whereas resonance tuning to the first‐order mode does not affect the electron transport. Here, the system is still in a weak coupling regime. These results are further correlated by experimental dispersion measurements and supported with transfer matrix simulations. The increase in electron mobility is not large due to high dissipation or low‐quality factors of the cavity modes. However, the mirrorless configuration presented here may offer a simpler way of boosting the properties of functional materials.

Mixed field radiation measurement using MOSFET sensor

We report here a study performed on MOSFET (Metal Oxide Semiconductor Field Effect Transistor) sensor for the measurement of accumulated doses from a mixed field radiations (especially gamma and fast neutron) environment such as nuclear detonation. The MOSFET sensor has shown its capability towards fast neutron dose measurement along with its well known gamma dose measurement capabilities. The study results are helpful in the establishment of MOSFET as a Personal Dosimeter for mixed field radiation. The measured sensitivities for gamma and fast neutron dose measurements are 1.1 mV/cGy and 0.6 mV/cGy respectively.

Optimizing the initial weights of a PID neural network controller for voltage stabilization of microgrids using a PEO-GA algorithm

This paper proposes an adaptive PID neural network (PIDNN) controller for direct and quadrature voltage control of three-phase inverters for islanded microgrids. A hybrid metaheuristic optimization algorithm is proposed for the initial weight selection of the proposed PIDNN controller using a discrete-time simulation model incorporating the nonlinearity of the insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) switches of the inverter. The proposed hybrid optimization (HO) approach is a combination of population extremal optimization (PEO) and genetic algorithm (GA). It turned out that the proposed HO-PIDNN control scheme excelled the PEO, GA, and particle swarm optimization-based PIDNN controllers in terms of the objective function value, which is composed of the integral time absolute tracking error of the output voltage and a chattering penalty factor. Also, the control system outperformed the model reference adaptive PID control technique from the literature.

Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability

To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (…2, 4, 2…) and (…2, 3, 2…) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device.

In vestigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics

The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.

Design and investigation of extended source F-type nano field effect transistor using non-equilibrium Green's function

In this manuscript, a novel semiconductor device termed an extended source F-type nano field effect transistor is proposed. The low bandgap material used at the source electrode is extended up to the drain electrode. At the drain electrode, extended material is confined by wide bandgap material to reduce the OFF-State current. For simulation, Schrodinger-Poisson equations are used to construct the Hamiltonian and non-equilibrium Green's function is used to evaluate the transport. For a thorough analysis, various materials are considered at source and drain electrodes. After investigation, the device is proposed with Si0.45Ge0.55 at the source electrode and SiC as confining material. The proposed device resulted in IOFF = 3.6 × 10−14 A/μm and ION = 8.27 × 10−4 A/μm. IDS-VGS characteristics are justified on basis of energy curve, transmission probability, and density of states at source and drain terminal. For the entire combination, device resulted in a subthreshold slope of approximately 60mV/dec. The proposed device can be used in the future to replace current field-effect transistors as it results in better characteristics than metal oxide semiconductor field effect transistors and will have a much simpler fabrication process than tunnel field-effect transistors.

Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell.

In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a metal-oxide semiconductor type graphene nano-ribbon field effect transistor (MOS-GNRFET) and compares the results with another SRAM cell designed using a PTM 10 nm FinFET node. Our simulations show that there is a change in the data stored in the SRAM after a heavy ion strike. However, it recovers from radiation effects after 0.46 ns for GNRFET and 0.51 ns for FinFET. Since the degradation observed in Q and Qb of GNRFET SRAM are 2.7X and 2.16X as compared to PTM nano-MOSFET, we can conclude that GNRFET is less robust to single effect upset. In addition, the stability of SRAM is improved by increasing the supply voltage VDD.

Design and Comparative Analysis of an Ultra-Highly Efficient, Compact Half-Bridge LLC Resonant GaN Converter for Low-Power Applications

For low-power applications, this paper presents the development and design of a compact and ultra-highly efficient half-bridge LLC resonant converter. By using Galium Nitride (GaN) devices and high-efficient magnetics, the efficiency and power density of resonant converters can be improved. Compared to Silicon MOSFETs, GaN high-electron-mobility transistors (GaN HEMT) have a lower output capacitance and gate charge, resulting in lower driving loss and shorter dead times. Consequently, the proposed LLC converter based on GaN devices has excellent performance characteristics such as ultra-high efficiency, low switching losses, compact size, high voltage endurance, high operating temperature and high operating frequency. Furthermore, the proposed resonant converter features soft switching properties that ensure that the switches and diodes on the primary side are always switched at zero voltage and current. By doing so, LLC resonant converter switching losses are significantly reduced by up to 3.1%, and an overall efficiency of 98.5% is achieved. The LLC resonant converter design with GaN HEMT has great advantages over Si MOSFET solution regarding efficiency, overall losses, switching loose and power factor correction. A 240 W, 240 V to 60 V half-bridge GaN HEMT LLC resonant converter is simulated with a switching frequency of 75 KHz, along with the comparative analysis of the Si metal oxide semiconductor field effect transistor (MOSFET) solution. Moreover, the design and analysis of highly efficient magnetics with a power factor of 0.99 at full load is presented. A 240-Watt single stage LED driver with power factor correction is also designed to verify and compare the performance of proposed LLC resonant converter.

Temperature and total ionizing dose effects of SiC MOSFET and their synergistic characteristics

In light of the extreme environmental conditions of temperature and radiation faced by silicon carbide Metal–Oxide-Semiconductor Field-Effect Transistor (SiC MOSFETs) in aerospace electronic systems, the damage characteristics induced by high-temperature stress and Total Ionizing Dose (TID) radiation were compared. Moreover, the synergistic effect of temperature stress and TID on the performance of SiC MOSFETs was studied. The impact of temperature stress and radiation on threshold voltage and static power current is consistent; However, the degradation trend of on-resistance is opposite. The research shows that after temperature stress removal, the change in device performance parameters can be recovered. The total ionizing dose radiation can cause permanent damage to the device; In the environment of temperature stress and radiation, the increase of temperature can weaken or restrain part of radiation damage.

Highly Efficient Three-Phase Bi-Directional SiC DC–AC Inverter for Electric Vehicle Flywheel Emulator

Flywheels are nowadays a solution for the dynamic charging of electric vehicles since they act as transient energy storage. The need for a top efficient reversible power converter for the flywheel system is crucial to assure high dynamic performance. The paper presents the design of a 50 kW highly efficient reversible three-phase DC–AC inverter involving the most recent silicon carbide metal oxide semiconductor field effect transistors, and its experimental validation on a home-made emulator. Highest efficiency in reversible mode, compactness, and thermal enhancement are the targeted objectives that have been achieved. The power converter prototype evaluated on an original pulse width modulation testing-bench is able to emulate the working of the flywheel system. High frequency pulse width modulation switching, speed cycle operating, and thermal losses are evaluated. In addition, an efficiency above 99% for the converter has been attained, enabling robust functioning of the flywheel system emulator to perform specific charging profiles for electric vehicles.

Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices.

Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator-metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 108.

Impact of an Underlying 2DEG on the Performance of a p-Channel MOSFET in GaN.

The influence of an underlying 2-dimensional electron gas (2DEG) on the performance of a normally off p-type metal oxide semiconductor field effect transistor (MOSFET) based on GaN/AlGaN/GaN double heterojunction is analyzed via simulations. By reducing the concentration of the 2DEG, a greater potential can be dropped across the GaN channel, resulting in enhanced electrostatic control. Therefore, to minimize the deleterious impact on the on-state performance, a composite graded back-to-back AlGaN barrier that enables a trade-off between n-channel devices and Enhancement-mode (E-mode) p-channel is investigated. In simulations, a scaled p-channel GaN device with LG = 200 nm, LSD = 600 nm achieves an ION of 65 mA/mm, an increase of 44.4% compared to a device with an AlGaN barrier with fixed Al mole fraction, ION/IOFF of ∼1012, and |Vth| of | - 1.3 V|. For the n-channel device, the back-to-back barrier overcomes the reduction of ION induced by the p-GaN gate resulting in an ION of 860 mA/mm, an increase of 19.7% compared with the counterpart with the conventional barrier with 0.5 V positive Vth shift.

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10<sup>-17</sup> farads and 1.11x10<sup>-12</sup> seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

An Online Junction Temperature Monitoring Method for SiC MOSFET Based on Drain-source Voltage Change Rate During Turn-on Transient

This paper analyzes the turn-on transient of silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) based on the basic physical equation, and the analysis model of drain-source voltage change rate (dv ds/dt ) during turn-on transient is derived. The change rule of dv ds/dt of SiC MOSFET during turn-on transient and its temperature-dependent characteristics are studied, and the calculations generally fit the measurements well. Experimental results show that the magnitude of turn-on dv ds/dt increases with increasing temperature and exhibits good linearity. The influence of driving conditions on the temperature dependence of the turn-on dv ds/dt is also analyzed through the model, finding that the temperature sensitivity can be improved by reducing the driving forward bias voltage and increasing the driving resistance. Finally, the online junction temperature monitoring experiments are used to verify the accuracy and effectiveness of the proposed method.

Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node

SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

High frequency single crystalline diamond MOSFET with high temperature (300 °C) ALD grown Al2O3 dielectric

In this paper, hydrogen terminated metal oxide semiconductor field effect transistors (MOSFETs) having a sub-micron gate length were fabricated on a single crystalline diamond sample using the 300 °C ALD grown Al2O3 as gate dielectric and passivation layer. The device shows a maximum output current density of 942 mA/mm and a lowest on-resistance of 6.2 Ω·mm at a VGS of −3 V. A maximum transconductance of 284 mS/mm was achieved. In addition, a high cut-off frequency of 41.3 GHz and a maximum oscillation frequency of 80.6 GHz were achieved. These are the highest values among the reported H-diamond MOSFETs with high temperature (>200 °C) grown dielectrics. The hole mobility is estimated to be 138 cm2/Vs at VGS = -3 V. The high carrier mobility contributes to the achievement of the high output current density. These results demonstrate that the high temperature grown Al2O3 dielectric has also a great potential to be used in high frequency H-diamond MOSFETs.