Metal-insulator-semiconductor Tunnel Diode Research Articles

Unveiling Sub-60 mV/decade Subthreshold Swing in The Oxide Local Thinning (OLT) Gated MIS Tunnel Diodes by TCAD Simulations

Metal-insulator-semiconductor (MIS) tunnel diodes (TD) are widely used in the modern integrated circuit, for its ease of fabrication and low cost. Recently, we have reported that the gated MIS TDs can exhibit sub-60 mV/decade subthreshold swing (SS) [1], which can be further reduced by introducing oxide local thinning (OLT) regions. SSs could be as low as 9.7 and 8.4 mV/decade in gated MIS TDs with the OLT regions formed by soft breakdown and photolithography, respectively [2,3]. The reason is unclear and the feasibility of scaling is of interest. In this work, we unveiled the mechanism and designed the scaled devices with ultra-low SS by TCAD simulation.We performed Silvaco TCAD with the 2-D cylindrical structure identical to [2] (Fig. 1). Models of direct tunneling and quantum confinement were included. The OLT region at the center TD is 100 nm. The OLT region at the gate is 400 μm from the inner gate edge, and the width (W GOLT) varies from 100 to 1000 nm.Fig. 2(a) shows the simulated I TD-V G curves of the OLT gated MIS TDs, denoted as TDOLT+GOLT, with different W GOLT, compared to the one without an OLT region at the gate, denoted as TDOLT, and Fig. 2(b) shows the corresponding SS. TDOLT+GOLT turns-on steeply, with SS approaching 10 mV/decade, close to the value observed in [2,3]. The electron densities n e at 2 nm depth in the silicon under different V G are examined for TDOLT and TDOLT+GOLT with W GOLT = 100 nm in Fig. 3(a) and (b) respectively. n e near the inner gate of the latter case increases abruptly from -0.8 to -0.7 V, due to the injection of the extra electrons from the gate OLT region. Fig. 3(c) shows the electron densities at 2 μm inside the gate edge for different devices, following the similar trend with the I TD-V G curves, indicating that the magnitude of the TD current is determined by n e near the gate edge. Fig. 4 shows the mechanism of TD current under different situations. For V G = -1 V, I TD is off and comes from the generation of electrons under the TD. For V G = -0.5 V, I TD is in the stage 1 and comes from the injection of electrons through the gate OLT region. The injection of electrons results in the steep increase of I TD and subsequently the ultra-low SS. For V G = 0.2 V, I TD is in stage 2 and collects the electrons generated in the whole substrate. The rapid increase of n e at the gate edge can be understood in another point of view. Fig. 5 shows the band diagram laterally near the silicon surface. Since n e depends on the difference between the conduction band energy (E C) and the electron quasi-Fermi level (E Fn), when V G increases from -0.8 to -0.7 V, E C is pushed down while E Fn at the gate edge is pulled up due to the injection of electrons through the gate OLT region. Therefore, the device can have SS lower than 60 mV/dec.To test whether the ultra-low SS characteristics can maintain when scaling down, we performed the simulation of the sub-micro device shown in Fig. 6. We find the TD cannot be turned off if we still use substrate thickness t sub = 5 μm (Fig. 7(a)), since the injection of electrons are too strong. However, by reducing t sub, I TD can be turned off and shows superior performance with on-off ratio over 8 orders and SS lower than 60 mV/decade (Fig. 7(b)). Since the electron diffusion current flowing to the substrate of an MIS TD with the substrate much shorter than the diffusion length can be expressed as J n = (qD n n i 2/t sub N A) e qΔΦ n/kT where q, D n, n i, N A, ΔΦ n, k, T are the elementary charge, electron diffusion coefficient, intrinsic carrier concentration, p-type doping concentration, electron quasi-Fermi level splitting, Boltzmann constant, and temperature, respectively, reducing t sub can lead to a stronger diffusion of electrons to the substrate, and there will be fewer electrons flowing to the gate edge (Fig. 8). Therefore, the electron densities can be lower near the gate edge when V G is negative enough, as shown in Fig. 9, leading to the effective turn-off of the TD.REFERENCES[1] Liao, et al., IEEE Trans. on Electron Devices, 62(6), 2061, (2015).[2] Yang, et al., IEEE Trans. Electron Devices, 66(1), 279, (2018).[3] Chiang, et al., IEEE Trans. Electron Devices, 67(4), 1887, (2020).ACKNOWLEDGEMENTThis work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-002-192-MY3 and NSTC 111-2622-8-002-001. Figure 1

Unveiling Sub-60 mV/decade Subthreshold Swing in The Oxide Local Thinning (OLT) Gated MIS Tunnel Diodes by TCAD Simulations

In this study, we unveil the sub-60 mV/decade subthreshold swing (SS) characteristics observed in the oxide local thinning (OLT) gated p-type metal-insulator-semiconductor (MIS) tunnel diodes (TD) utilizing TCAD simulations. Through our simulations, we successfully replicate the sub-60 mV/decade SS behavior and attribute this remarkable characteristic to the rapid increase in electron density near the gate edge. This phenomenon arises from electron injection through the gate OLT region under a negative gate voltage, leading to a significant elevation in electron density near the gate edge. Armed with this insight, we design scaled devices to assess the feasibility of achieving sub-60 mV/decade SS behavior. By modulating the substrate thickness, we effectively simulate devices with SS lower than 60 mV/decade across a current range spanning 8 orders of magnitude.

Enhancement of Transient Current in MIS(p) Tunneling Diode with Reduced Reversed Bias Current by Oxide Removal at the Gate Edge

Transient behavior plays a critical role in electronic devices since it represents the potential to serve as memory applications. Recently, some transient current behavior of metal-insulator-semiconductor tunnel diode (MISTD) has been demonstrated with unconventional structures [1], [2]. However, due to the usage of multiple photomasks and the process complexity at the gate edge, these devices may have scale-down issues in advanced CMOS-compatible processes. In this work, a structure of edge-removed (ER) MISTD has been proposed. Compared to previous work [2], which removes surrounding oxide and Si substrate by trench forming, the ER MISTD improves the device performance by not damaging the Si substrate. The ER MISTD can remain the same transient current window (CW) while being operated at smaller write voltage and device area. With the advantages of a smaller device area, energy-efficient operations, and the simplicity of the fabrication process, the ER MISTD is promising to serve as dynamic memory applications.The schematics of the conventional co-planar and ER MISTD are shown in Fig. 1. With the removal of the surrounding gate oxide, ER MISTD demonstrates not only lower reverse bias current but also hysteresis displacement current in Fig. 2(a) compared to planar MISTD. The leakage current of ER MISTD is 3 orders of magnitude smaller than that of planar MISTD at VG = 2V. Fig. 2(b) shows the high-frequency capacitance-voltage measurement, which demonstrates enlarged deep depletion region of the ER MISTD. We further investigated the phenomenon by Sentaurus TCAD as shown in Fig. 3. The existence of oxide charges was also adopted in simulation. The deeper depletion phenomenon of ER MISTD can be attributed to the lack of minority carriers and oxide charges without the existence of surrounding gate oxide. Another evidence of the lack of minority carriers is shown in Fig. 4. The saturation current of ER MISTD remains lower while that of planar MISTD increases and eventually induces oxide breakdown around VG = 5V. It is also found that ER MISTD isn't in oxide breakdown when VG is over 40 V as shown in the inset of Fig. 4.Next, the enhanced two-state transient current behavior has been demonstrated in Fig. 5. The specific measurement steps are shown in the inset of Fig. 5(a) and 5(b). ER MISTD has better CW in both operations compared to planar MISTD. We further investigated the mechanism of the two operations.When VG is switched from 1V to 0V, the minority carriers (𝑄𝑖𝑛𝑣) would become excess carriers since no enough time for them to be recombined. Because ER MISTD has an insufficient supply of minority carriers due to the absence of gate edge fringing field, the electron tunnel current generated by excess carriers is smaller compared to planar MISTD. With a smaller electron tunnel current to compensate for the transient discharging current, the total transient read current of ER MISTD is larger than that of planar MISTD.When VG is switched from -0.5V to 0V, the depletion region is suddenly expanded and therefore generates extra displacement current. Since the change of depletion width of ER MISTD is larger, the positive displacement current is larger as well. Because the transient current is the summation of the positive discharging current and displacement current, the transient current of ER MISTD is larger.The endurance measurement of ER MISTD has been examined as shown in Fig. 6. Fig. 6(a) shows the endurance can be tested up to 5000 cycles between 1V and 0V without much degradation. Fig. 6(b) shows the endurance between 1V and -0.5V with 102 cycles.We further investigated the CW of two operations corresponding to oxide thickness. As shown in Fig. 7, when oxide becomes thicker, the transient behavior becomes larger due to the decrease of the tunneling probability. However, the CW would eventually decay when the oxide is too thick. This is because tunnel current will disappear at thicker oxide, the transient behavior is therefore reduced. The peak value of the CW is around EOT = 3.1 nm.In conclusion, ER MISTD shows enhanced transient current and reduced leakage current due to the enlarged deep depletion. We also proposed two-state memory operations and endurance measurement of ER MISTD. The correspondence of CW and oxide thickness has been investigated as well. Because of the above characteristics, ER MISTD shows its potential to serve as a dynamic memory application.Reference:[1] Huang S -W and Hwu J -G 2021 IEEE Trans. Electron Devices 68 6580-6585[2] Lin J -Y and Hwu J -G 2021 IEEE Trans. on Electron Devices 68 4189-4194 Figure 1

Influence of Outer Oxide Charges on the Electrostatics of Metal-Insulator-Semiconductor Tunnel Diode

Metal-Insulator-Semiconductor Tunnel Diode (MISTD) has an ultra-thin oxide with thickness less than 3.5 nm. When a MISTD is biased higher than a critical voltage V C, the device will be driven into the deep depletion region [1]. In this biasing condition, the electrostatics of the device will deviate from the behavior of traditional metal-oxide-semiconductor capacitors with thick oxide [1]. Thus, finding out the critical voltage V C is important to predict the electrostatics of a MISTD. In this work, we found that there is a systematic deviation of V C between the theoretical and the experimental values. A model considering the oxide-charge-induced lateral coupling (OCILC) is suggested as a possible mechanism leading to the deviation. With adding effective positive oxide charges of Q eff/q = 2.4-2.6×1011 cm-2, the calculated V C can fit well with the experimental observations.Figs. 1(a) and (b) are the band diagrams of MISTD biased at V TD < V C and V TD > V C, respectively, where V TD is the positive voltage applied on the metal. When V TD < V C, the generated electrons flow -J gen,bulk are able to follow the increase in the inversion charges and leakage current -J tunnel. In this situation, most of the applied V TD drops on the oxide, and the surface band bending of the silicon ψ s keeps around its initial value ψ 0, as shown in Fig. 1(a). In contrast, at V TD > V C, the generated electrons in original depletion region cannot follow the increase of the tunneling current. To keep the balancing of -J tunnel = -J gen,bulk, a large portion of V TD drops on the silicon and leads to an intense increase in ψ s, as shown in Fig. 1(b). The MISTD will operate under a significant non-equilibrium region under this bias condition. The balancing of -J tunnel = -J gen,bulk is finely discussed in [1].Ten MISTDs with distinct oxide thicknesses ranging from 23.7 to 34.4 Å were fabricated to extract V C. The device structure is shown in Fig. 2(a). The shape of the device is a circle with a diameter of 170 µm. From the measured high-frequency capacitance-voltage (HFCV) relations shown in Fig. 2(a), one can observe a flat region before a critical voltage and a quick decrease after the critical voltage. One can further extract surface band bending ψ s by HFCV [2]. The extracted q∆ψ/kT = q(ψ s-ψ 0)/kT is plotted in Fig. 2(b), where ∆ψ is the difference between ψ s and ψ 0. As the definition in [1], we extract V C at q∆ψ/kT = 3. The extract V C v.s. t ox is shown in Fig. 3 as solid symbols. At the same time, theoretical V C from the modeling proposed in [1] is also attached as a solid line. From Fig. 3, we observed a significant difference in V C between the modeling and the experimental.It is suggested that the OCILC causes the deviation of V C. The mechanism of OCILC is plotted in Fig. 4(a). The positive oxide charges outside the electrode will attract electrons at the silicon surface and form a lateral coupling channel. The potential applied on the electrode will laterally transport through the channel and collect the generated electrons from the lateral region. Finally, the balancing of electrons will become -J tunnel = -J gen,bulk-J gen,lateral, as shown in Fig. 4(b). Because of the extra supplement of electrons (-J gen,lateral), the MISTD can hold the quasi-equilibrium status to a higher voltage, and the V C increase. An improved model considering the effect of OCILC is proposed. The calculated result is plotted in Fig. 5. One can observe V C increase with Q eff. When positive Q eff/q is around 2.4-2.6×1011 cm-2, the calculated V C is close to the V C extract from the experimental.In conclusion, we suggested that the oxide charges outside the electrode play an important role in the electrostatics of MISTD. The mechanism of OCILC is proposed to explain the impact. A model considering OCILC is developed to calculate V C and the results fit well with the experimental results.This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and the National Science and Technology Council of Taiwan, ROC, under Contract No. NSTC 111-2622-8-002-001.[1] K. W. Lin, K. C. Chen and J. G. Hwu, An Analytical Model for the Electrostatics of Reverse-Biased Al/SiO₂/Si(p) MOS Capacitors With Tunneling Oxide, IEEE Trans. Electron Devices, 69, 1972, (2022)[2] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley, Hoboken) (1982) Figure 1

Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)

Metal-Insulator-Semiconductor tunnel diodes (MISTD) are widely used in modern integrated circuits, and have shown the potential in dynamic memory [1], [2]. To recognize the memory states more easily, efforts should be made to enhance the transient behavior. Recently, MISTD with ultra-thin metal surrounded gate (UTMSG) had been proposed in [3] and [4], presenting improved transient current and transient capacitance. In this work, we further modulated the proportion of surrounding gate, S, and found increased transient behavior for larger S.Fig. 1(a) and (b) illustrate the structure of UTMSG and planar MISTD, respectively. For UTMSG, the total gate is composed of a thick metal center gate and a resistive thin metal surrounding gate. Fig. 2 shows the process flow and the anodic oxidation system. For UTMSG, after defining the center gate by photolithography, dilute nitric acid was used to form a very thin aluminum oxide layer on the edge. 10 nm Al was then evaporated as the resistive surrounding gate. Table 1 lists the detailed parameters and the proportion of surrounding gate, S. Fig. 3(a) shows the transient read currents for UTMSG and planar, with inset illustrated the voltage program. Fig. 3(b) shows the read currents extracted at 40 ms under different read voltages after a 2 V write pulse. All UTMSG show larger transient current than planar. Besides, UTMSG with larger S would have better performance. The reason could be explained by Fig. 3(c). The insulating aluminum oxide interlayer and the resistive thin metal surrounding gate together result in a distributed resistance, leading to an RC time delay during voltage switching. During read, the electrons stored under the surrounding gate would take longer to response. Therefore, larger current could be read out, due to the edge late response. Consequently, more electrons would be delayed for larger S, and larger transient current would be expected.Fig. 4(a) and (b) show the AC signal model and the reverse-bell shape capacitance-voltage (C-V) characteristics of UTMSG, which were discussed in detail in previous work [5]. When Rsi, determined by the electron density under gate, is small enough such that the cut-off frequency 1/2πRsiCs,o is larger than the AC frequency, Cs,o could be read out. Fig. 5 shows the frequency dispersion of C-V curves. For lower frequencies, lower VG is needed for the AC signal to pass through.Fig. 6(a) shows the 10kHz C-V curves, on which ± 0.5 V voltage pulse were performed to read out two capacitance states. Fig. 6(b) shows the transient capacitance read at 0 V. When switching from + 0.5 V to 0 V, excess electron would be stored under gate initially. To balance the gate voltage, depletion region would shrink and high capacitance state would be measured, which would be more significant for UTMSG due to more delay of electron. For UTMSG at – 0.5 V and 0 V, depletion capacitance under center gate Cs,i and under total gate Cs,i + Cs,o would be read out, respectively. This means after applying a - 0.5 V pulse and then read at 0 V, UTMSG devices would experience a larger change of capacitance. Moreover, since the capacitance at - 0.5 V is lower for UTMSG with larger S, the change of capacitance would be larger. The two state capacitance windows measured at 30 ms are shown in Fig. 6(c), where larger capacitance window could be observed for UTMSG with larger S. Finally, the capacitances when sweeping voltage forwardly and backwardly and the separation between them were shown in Fig. 7(a) and (b) for UTMSG and planar devices. All UTMSG show larger separations, which further confirms the improved transient capacitance window observed in Fig. 6.In conclusion, transient behavior could be further improved by increasing the proportion of surrounding gate in UTMSG MISTD, and 17x read current and 14x capacitance window could be measured. The discovery in this work might be beneficial for the future dynamic memory design.Acknowledgement: This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and NSTC 111-2622-8-002-001[1] M. A. Green, F.D. King and J. Shewchun, Solid-State Electronics, 17, 6, pp. 551-561, (1974).[2] S.-W. Huang and J.-G. Hwu, IEEE Trans. on Electron Dev., 68, 12, pp. 6580-6585 (2022).[3] K.-H. Tseng, C -S. Liao and J. -G. Hwu, IEEE Trans. on Nanotech., 16, 6, pp. 1011-1015, (2017).[4] C.-D. Lin and J.-G. Hwu, ECS Trans., 85, 51, (2018).[5] S.-W. Huang and J.-G. Hwu, IEEE J. of the Electron Devices Soc., 9, pp. 1041-1048, (2021). Figure 1

Enhancement of Transient Current in MIS(p) Tunneling Diode with Reduced Reversed Bias Current by Oxide Removal at the Gate Edge

In this work, the transient current behavior of metal-insulator-semiconductor tunnel diode (MISTD) with oxide removal at the gate edge has been investigated. With an oxide-removed structure at the gate edge, the edge-removed (ER) MISTD not only exhibits reduced reverse bias current but also demonstrates enhanced transient current compared to conventional co-planar MISTD. These improved characteristics of ER MISTD can be attributed to the absence of oxide charges outside the gate edge and the insufficient supply of minority carriers. We also proposed a two-state transient current operation and tested the device’s endurance. Finally, we examined the relationship between oxide thickness and the current window and found that the current window is maximum when EOT is around 3.1 nm. Based on these properties, edge-removed MISTD shows potential as a dynamic transient memory device.

Influence of Outer Oxide Charges on the Electrostatics of Metal-Insulator-Semiconductor Tunnel Diode

In this work, the impact of outer oxide charges on the electrostatics of metal-insulator-semiconductor tunnel diodes (MISTD) is discussed. The existence of outer oxide charges will significantly affect the critical voltage V c of MISTD in the strong inversion region. At the bias voltage of V < V c, the MISTD works like a traditional metal-oxide-semiconductor (MOS) capacitor. However, at the bias voltage of V > V c, the MISTD goes to deep depletion. V c is an important boundary for the electrostatics behavior of MISTD. We propose a model, considering the existing outer oxide charges, to calculate V c and compare the calculated results with V c extracted from our devices. V c of our devices is extracted by measuring high-frequency capacitance-voltage (HFCV) at 300 kHz. It is found that the model is able to fit well with the experimental results when the amount of outer oxide charges is in the magnitude of 2.5×1011 cm-2 for our devices. The model is fundamental but helpful for analyzing and designing a MISTD.

Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)

Transient behavior of metal-insulator-semiconductor tunnel diode (MISTD) with ultra-thin metal surrounded gate (UTMSG) is discussed in this work. The influence of an important parameter, S, which is the area proportion of surrounding gate to the total gate, on the transient read current and transient capacitance window is demonstrated. Transient current is found to be larger for larger S due to more significant edge late response. By taking advantage of the unusual capacitance-voltage characteristics, improved capacitance window could be achieved. The transient current window and capacitance window of UTMSG device with S = 0.66 have been found to be 17x and 14x larger compared with planar device.

Improved Two States Characteristics in MIS Tunnel Diodes by Oxide Local Thinning Enhanced Transient Current Behavior

The effect of oxide local thinning (OLT) on the increase in current two states in metal–insulator–semiconductor (MIS) tunnel diodes for dynamic memory usage has been demonstrated. Two orders of magnitude improvement in the read current window could be observed. The MIS sample after performing the deep depletion stress (DDS) would soft breakdown (SBD) and could be effectively considered that the oxide was locally thinned. Pulsed voltage program was used to write on fresh MIS (before SBD) and OLT MIS (after SBD). A larger magnitude of transient read current could be observed for OLT MIS, and subsequently the improved current two states characteristics. The read currents of OLT MIS were stable under the endurance test. The transient behavior of a fresh MIS could be understood by the charging and discharging of a capacitor. On the contrary, the tunneling current would be dominated in an OLT MIS. At the same time, since the electron tunneling only concentrated locally, OLT MIS would take longer to recover to the steady-state. The improvement of read current after OLT forming was reproducible, and various write programs were performed for further examination. TCAD simulations demonstrated that the electrons would leak out and the electron density would decrease under larger gate voltage for OLT MIS. This work has shown the potential of OLT MIS for the dynamic memory usage, and the idea of local thinning on the gate oxide might be beneficial for the design of the future dynamic memory.

Transient Current Enhancement in MIS Tunnel Diodes With Lateral Electric Field Induced by Designed High-Low Oxide Layers

In this work, the steady-state and transient behavior of the metal–insulator–semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application.

Enhanced Transient Behavior in MIS(p) Tunnel Diodes by Trench Forming at the Gate Edge

In this article, a new type of metal-insulator-semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current-voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance-voltage (C-V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices.

Role of Schottky Barrier Height Modulation on the Reverse Bias Current Behavior of MIS(p) Tunnel Diodes

Current and capacitance characteristics of Al/SiO2/Si(p) metal-insulator-semiconductor tunnel diode (MISTD) with oxide thickness in the range of about 2-4 nm were fabricated and studied in detail in this work. We found that the saturation reverse bias current will increase with oxide thickness in this range of oxide thickness. This non-intuitive phenomenon is caused by different levels of Schottky barrier height modulation (SBHM), which leads to the injection of the majority from metal. The majority current of Al/SiO2/Si(p) MISTD is usually neglected because of the blocking of the oxide layer and the Schottky barrier. The mechanism and numerical analysis of SBHM are discussed in this work. SBHM is significant when the oxide is thin enough for the majority to tunnel from metal to semiconductor and thick enough to hold a part of the minority inversion layer. In this specific oxide thickness range, increasing oxide thickness will increase the ability to hold the inversion layer, thus leading to higher oxide voltage (Vox) and stronger SBHM. As a result, we find that stronger SBHM lets more majority have enough energy to inject from metal to semiconductor and cause higher reverse saturation current in MISTD with thicker oxide. With the numerical analysis in our work, we also predict this non-intuitive phenomenon will start to turn around when oxide thickness is thicker than about 33Å. This phenomenon indicated that majority current is an un-neglectable component when the oxide is thick enough to hold the inversion layer partially. The analysis in this work is also helpful to complete the missing part of the theory describing the current behavior of MISTD.

Transient Two-State Characteristics in MIS(p) Tunnel Diode with Edge-Thickened Oxide (ETO) Structure

In this work, the transient two-state characteristics of edge thickened oxide (ETO) metal-insulator-semiconductor (MIS) tunnel diodes with various gate electrode areas were studied. The ETO MIS structures were first compared with the planar MIS structures to prove their transient memory potentials and then were simulated by TCAD to find out the mechanism of them. By TCAD simulation, it was focused that there is a lateral electric field built at the boundary of thin and thick oxides in ETO structure. The ETO MIS structures with various gate electrode areas were compared to find out the relation between the gate area and the transient memory performance. ETO MIS structure with proper gate electrode area was suggested for large transient application.

Coupling sensitivity in concentric metal–insulator–semiconductor tunnel diodes by controlling the lateral injection electrons

Coupling sensitivity between two Al–SiO2–pSi metal–insulator–semiconductor tunnel diodes (MISTDs) was examined by sweeping bias voltage on one MISTD and detecting ground current or floating voltage at another nearby MISTD with the substrate being grounded when performing the measurement. A strong coupling phenomenon between two concentric MISTDs was observed in this work. The experiment shows that the coupling sensitivities have a maximum value at a range of about −0.4 V to −0.7 V and turn to minimum at about the flat band voltage (∼−0.9 V) when bias was swept from 0 to −1 V. The simulation result also shows a maximum lateral diffuse current when the MISTD was biased at about −0.7 V and turns to a small value near the flat band voltage. It was speculated that the lateral electron flow due to piled-up injection electrons is the origin of the observed highly sensitive coupling phenomenon. A possible mechanism was proposed to explain the turnaround phenomenon.

Ultra-Low Subthreshold Swing in Gated MIS(p) Tunnel Diodes With Engineered Oxide Local Thinning Layers

In this article, oxide local thinning (OLT) effects on the performance of a gated metal–insulator–semiconductor tunnel diode (MIS TD) with a p-type substrate were demonstrated through the fabrication of well-defined OLT regions at the gate and the drain. Without soft breakdown treatment of the oxide layer as reported before, the designed OLT patterns give rise to such devices to be of particular use. Specifically, sub-60 mV/decade subthreshold swing (SS) in the transfer characteristics was achieved with OLT regions at the device gate, while the operating voltage, as well as SS, could be further reduced with those at the drain. Moreover, by adjusting the number and area of OLT regions that are evenly distributed within the device, SS could be possibly optimized to a much lower value, e.g., 8.4 mV/decade, over three current decades. The enhanced lateral transport efficiency of minority carriers from the gate to the drain, which leads to the ultra-low SS, is attributed to the OLT region as an extra energy source under negative bias with its effectiveness depending on the area and thicknesses of both the relatively thick and thin oxides. The roles of these physical parameters were investigated using 2-D TCAD simulation and evidenced by experimental results.

Improved Low-Voltage Sensing Performance in MIS(p) Tunnel Diodes by Oxide Thickening at the Gate Fringe

The effect of selective-area oxide thickening in metal–insulator–semiconductor (MIS) tunnel structures on their current–voltage characteristics was investigated in this article. Under a low applied voltage ( $> 100\times $ with respect to the device with thin-only oxide, and so was the photocurrent $> 100\times $ larger under an illuminance of 100 lx. With such an improved sensing performance, the ET MIS tunnel diode may find its use in low-cost sensor applications.

Edge-Etched Al2O3 Dielectric as Charge Storage Region in a Coupled MIS Tunnel Diode Sensor

The effects of an Al2O3 dielectric patterned by wet etching in a metal-insulator-semiconductor (MIS) tunnel diode are studied by I-V, C-V and charge storage characteristics in this paper. The behaviors are obviously different from the device without an etched edge. It is suggested that traps are formed at the edge because of the etching process. A circuit model is proposed to explain the effect of the existence of additional traps. With the etched edge as charge storage region, current ratio of programmed and erased states of the tunnel diode sensor is expanded for 165 times and the retention characteristic is much improved. Meanwhile, charge storage characteristic varies with the thickness of the Al2O3 dielectric. Multilevel demonstration is carried out by specified programming process which is not feasible on coupled MIS previously. In addition, relation between the sensing current and stress conditions is examined. A maximum on/off ratio of 105 is achieved. The study of the etched edge is believed to be beneficial for future development in memory cell constructed by MIS TD.

High rectification ratio metal-insulator-semiconductor tunnel diode based on single-layer MoS2

Single-layer MoS2, with its ultimate atomic thickness, has shown promise to scale down transistors for modern integrated circuitry. On the way to implementing two-dimensional (2D) electronic devices, controlled wafer-scale synthesis of single-layer MoS2, single-layer MoS2 metal-oxide-semiconductor field-effect transistors, ohmic contact of single-layer MoS2 for low contact resistance, etc, have been extensively studied. However, the most commonly used two-terminal electronic component, a diode, which conducts current primarily in one direction, has rarely been reported based on single-layer MoS2. Here, a two-terminal high rectification ratio metal-insulator-semiconductor (MIS) tunnel diode was reported based on single-layer MoS2. The In/Au (10/70 nm) electrode via thermal evaporation was used to form a good ohmic contact with the single-layer MoS2. The Si3N4/Pd/Au (5/10/70 nm) electrode via electron beam evaporation was used to form an MIS tunneling structure with the MoS2, showing a current rectification ratio of up to 107 at room temperature. The high current rectification ratio is realized by controlling the quantum tunneling carrier density and the tunneling barrier width. The single-layer MoS2 MIS tunnel diode fabricated via the silicon technology compatible evaporation method has potential application as a fundamental electronic building block for future 2D electronics.

Effect of Oxide Thickness on The Two-State Characteristics in MIS(p) Tunnel Diode with Ultrathin Metal Surrounded Gate

In this work, the transient two-state currents of ultrathin metal surrounded gate (UTMSG) metal-insulator-semiconductor (MIS) tunnel diodes, in which the periphery portion of the gate metal thickness is about 10 nm, with various oxide thicknesses were studied. The electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate metal-insulator-semiconductor (RG MIS) tunnel diodes with various oxide thicknesses were compared and it was found that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses range of 27 Å ∼ 30 Å. The electrical properties of the UTMSG MIS devices are very sensitive to oxide thickness. Also, it was found that the I-V current hysteresis is closely related to the transient two-state characteristics because of the RC delay at edge.

Light-to-Dark Current Ratio Enhancement on MIS Tunnel Diode Ambient Light Sensor by Oxide Local Thinning Mechanism and Near Power-Free Neighboring Gate

A charge coupled metal insulator semiconductor (MIS) tunnel transistor after self-protective oxide breakdown process was used for ambient light sensing. The drain part of the transistor is an MIS tunnel diode (TD) with ultrathin oxide, which collects the light and dark currents. A surrounding MIS gate with thicker oxide is placed beside the drain at a distance smaller than $1~\mu \text{m}$ by the method of controlling the undercut of wet etching. Under illumination, the transfer curve of the transistor shows a low subthreshold swing smaller than 60 mV/decade due to the aid of photoemission to the double-exponential mechanism controlled subthreshold current. The device after drain breakdown process shows significant enhancement of light-to-dark current ratio comparing to either single MIS TD or the same structure without breakdown. Also, no additional power is included with the added gate voltage because of the low leakage gate structure. Comparing to the case without gate voltage, the maximum light-to-dark current ratio at a suitable gate voltage shows lower power dissipation, which meets the need of low-power requirement in nowadays’ electronic devices.