Abstract
The effects of an Al2O3 dielectric patterned by wet etching in a metal-insulator-semiconductor (MIS) tunnel diode are studied by I-V, C-V and charge storage characteristics in this paper. The behaviors are obviously different from the device without an etched edge. It is suggested that traps are formed at the edge because of the etching process. A circuit model is proposed to explain the effect of the existence of additional traps. With the etched edge as charge storage region, current ratio of programmed and erased states of the tunnel diode sensor is expanded for 165 times and the retention characteristic is much improved. Meanwhile, charge storage characteristic varies with the thickness of the Al2O3 dielectric. Multilevel demonstration is carried out by specified programming process which is not feasible on coupled MIS previously. In addition, relation between the sensing current and stress conditions is examined. A maximum on/off ratio of 105 is achieved. The study of the etched edge is believed to be beneficial for future development in memory cell constructed by MIS TD.
Highlights
Several applications such as solar cells, temperature sensors and memory devices [1]–[4] are carried out by metaloxide-semiconductor (MIS) tunnel diodes because their oxide-tunneling currents are highly sensitive to surrounding signals
It should be noted that the sensing voltage must be large enough for drain MIS tunnel diode (TD) to enter its saturation region, so its current can be modulated by the minority carrier supply
The edge-etched MIS (EE MIS) owns a medium current level which is bizarre if only direct tunneling mechanism is considered
Summary
Several applications such as solar cells, temperature sensors and memory devices [1]–[4] are carried out by metaloxide-semiconductor (MIS) tunnel diodes because their oxide-tunneling currents are highly sensitive to surrounding signals. Charges can be captured by the defects existed in the Al2O3/SiO2 by voltage stress and give rise to memory phenomenon [11] Defects such as Al vacancies (VAl), oxygen vacancies (VO), Al interstitials (Ali), and oxygen interstitials (Oi) in the Al2O3 dielectrics are located at or near the interface [12], [13]. After a negative voltage defined as program is stressed on gate, electrons are trapped in the dielectric edge (Fig. 2(a)). It should be noted that the sensing voltage must be large enough for drain MIS TD to enter its saturation region, so its current can be modulated by the minority carrier supply. Because of the trapped electrons, the band bending beneath gate edge is smaller at floating and less electrons are induced This results in the reduction of Fe. As a consequence, the qφh∗ in equation (1) becomes larger and a minor current is sensed at drain (Fig. 2(b)). The thickness of Al2O3 dielectric is a factor affecting the memory performance and is discussed
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