Gate Metal Deposition Research Articles

Realization of dual-gated Ge–SixGe1−x core-shell nanowire field effect transistors with highly doped source and drain

We demonstrate dual-gated germanium (Ge)-silicon germanium (SixGe1−x) core-shell nanowire (NW) field effect transistors (FETs) with highly doped source (S) and drain (D). A high-κ HfO2 gate oxide was deposited on the NW by atomic layer deposition, followed by TaN gate metal deposition. The S and D regions of NW were then doped using low energy (3 keV) boron (B) ion implantation with a dose of 1015 cm−2. The electrical characteristics of these devices exhibit up to two orders of magnitude higher current and an improved ON/OFF current ratio by comparison to dual-gated NW FET with undoped S/D.

Device Characteristics of AlGaN/GaN MOS-HEMTs Using High-$k$ Praseodymium Oxide Layer

In this brief, AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) using an electron-beam-evaporated praseodymium oxide layer (Pr2O3) in a high-oxygen-flow environment during the gate-dielectric-layer formation was studied. By adjusting the oxygen flow rate in an electron-beam evaporator chamber, the highest Pr content in Pr2O3 occurred at 15 sccm. Moreover, the Pr2O3 thin film also achieved a good thermal stability after 400-degC, 600-degC, and 800-degC postdeposition annealing due to its high-binding-energy (933.2 eV) characteristics. The gate leakage current can be improved significantly by inserting this high- k dielectric layer, and meanwhile, the power-added efficiency can be enhanced up to 5%. Experimental results have also shown that Pr2O3 MOS-HEMTs outperformed the standard GaN HEMTs in output power density and in pulsed-mode operation. These high-performance electron-beam-evaporated Pr2O3 high-k AlGaN/GaN MOS-HEMTs are suitable for high-volume production due to its in situ insulator and metal-gate deposition in the same chamber.

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO 2 dielectric

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO 2 gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO 2 devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high- k stacks but higher than that for the poly-Si SiO 2 system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.

Effect of degas before metal gate deposition on the threshold voltage

The interaction between the dielectric and the metal gates is crucial for effective workfunction and V T. In this work, we investigate the effect of a degas step just before the metal gate deposition. The purpose of this step is to remove the water adsorbed at the surface of the dielectric by heating it under vacuum. Removing the water also means the suppression of an O source during following processing steps of the device. This leads to lower oxygen vacancies passivation. When the maximum of water is removed from the surface, NMOS long channel V T is decreased and PMOS long channel absolute V T is increased. From the dielectric point of view, degassing leads to lower intrinsic quality as measured by gate leakage increase as a function of the temperature.

Effect of Gate Sinking on the Device Performance of the InGaP/AlGaAs/InGaAs Enhancement-Mode PHEMT

An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degC for gate sinking. After the annealing, the device showed a positive threshold voltage (Vth) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 muA/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the Vth was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process

Work function engineering using lanthanum oxide interfacial layers

A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function.

Asymmetry in Gate Capacitance–Voltage$(C$–$V)$Behavior of Ultrathin Metal Gate MOSFETs With$hboxHfO_2$Gate Dielectrics

Anomalous asymmetry (which here means "beyond that to be expected classically") between accumulation and strong inversion was observed in the measured capacitance-voltage (C-V) curves of metal gate nMOSFETs with ~ 1 nm equivalent oxide thickness (EOT) HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers and was analyzed and extrapolated to still smaller devices and to pMOS devices using self-consistent Poisson-Schrodinger simulations. The experimental devices were fabricated via atomic layer deposition (ALD) of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> on stress-relieved preoxide (SRPO), followed by tantalum carbon alloy metal gate deposition. Simulations suggest two underlining mechanisms for this anomalous asymmetry, namely 1) differing degrees of quantum mechanical carrier penetration into the dielectric associated with the differing electron and hole barriers and 2) differing degrees of quantum confinement within the substrate, which result from differing electron and hole bandstructures in the Si. Both mechanisms result in greater capacitance when the quantum-confined surface carriers are electrons than when they are holes. Simulations indicate that this effect can produce asymmetries between pMOS and nMOS devices under strong inversion for the same physical gate stack that will become increasingly important as the trend toward smaller devices and use of high-kappa dielectrics continues: perhaps approximately 10% reduction in pMOS strong-inversion capacitance relative to that of nMOS devices for 0.5 nm EOT high-kappa gate stacks

Investigation of Molybdenum Nitride Gate on SiO2 and HfO2 for MOSFET Application

It has been reported that the work function of nitrided molybdenum (MoN) can be modulated by the atomic ratio of and is suitable for gate material of complementary metal oxide semiconductor devices. In this work, we investigated the characteristics of prepared by reactively sputtering deposition from the gate electrode point of view. The main phase of the films is MoN(200). As the ratio increases, the microstructure of film tends to be amorphous-like and the resistivity increases. After high-temperature annealing, the phase remains stable and grain size increases slightly. The film has better immunity to sputtering damage than film; therefore, the sputtering deposition method could be a choice of metal gate deposition as -based dielectric is used. The work function of increases with the increase of nitrogen content and tends to saturate at the valence band of Si. No Fermi-pinning effect is observed on film. The work function and thermal stability of show good thermal stability on both and films up to at least. All of these results indicate that MoN is a good candidate of gate electrode for p-type metal oxide semiconductor field effect transistors (pMOSFETs) or fully depleted SOI devices.

Study of metal gate deposition by magnetron sputtering

A systematic study on metal gate deposition by magnetron sputtering is presented. The authors compared the interface trap density (Dit) in metal-oxide-semiconductor capacitors with metal gate deposited by either conventional magnetron sputtering, atomic layer deposition followed by conventional sputter deposition, or a newly developed magnetron sputtering technology. The results indicate that the new sputtering technology can minimize plasma damage to the underlying ultrathin dielectric film and achieve Dit values of less than 1011cm−2eV−1⁠. Experimental data on plasma characterization using ion collectors and Langmuir probe are presented. The effects of metal gate deposition methods, dielectric film thickness, and sputtering parameters such as sputtering power, pressure, and pulsed dc sputtering are discussed. It is found that pulsed dc sputtering generates higher Dit values. In the new sputtering process, the flux and the energy of the ions arriving at the substrate surface are several times lower, and the floating voltage fluctuations on the substrate surface are about one order of magnitude lower, effectively preventing potential plasma damage to the underlying dielectric films by minimizing energetic particle bombardment and charging impact.

Self-aligned fabrication of single crystal diamond gated field emitter array

This paper describes a self-aligned fabrication process for diamond gated field emitter array (FEA). Utilizing the non-conformal coverage sputtering conditions of silicon oxide, an interesting “sphere on cone” structure is formed on diamond nano tip array, which is the key point of gate hole opening process. This structure causes shadowing at certain regions of side-wall during Ti / Au gate metal deposition. Removal of “sphere” by wet etching leads to the successful fabrication of a single crystalline diamond gated FEA. Scanning electron microscope observations reveal the fabrication of a uniform emitter array with tip radius of curvature (20 nm) and gate hole (1.4 μm). We also confirmed that no noticeable physical damage exists on tip. In field emission characteristics of the fabricated single crystal diamond gated FEA, gate voltage control of field emission current is realized.

Effect of the dielectric thickness and the metal deposition technique on the mobility for HfO2/TaN NMOS devices

In this paper the effects from the high-κdielectric thickness and the metal gate deposition technique on the mobility of n-channel MOS transistors are investigated. The results reveal mobility degradation due to an increase of charge density in the dielectric and / or at the material interfaces, not efficiently compensated by the screening effect from the gate. We correlate this mobility degradation to the reduction observed in a comparison between metal and poly-Si gated MOSFETs. It is shown that the mobility can be improved by using different metals deposition technique, which indicates that the mobility reduction is related to the deposition technique.

Impact of Metal Gate Deposition Method on Characteristics of Gate-First MOSFET with Hf-Silicate

This paper compares metal oxide semiconductor field effect transistor (MOSFET) characteristics of TiN metal gate deposited by atomic layer deposition (ALD) and chemical vapor deposition (CVD) on Hf-based high- dielectrics. Despite many similarities between these two techniques, clear differences were found in device characteristics such as equivalent oxide thickness (EOT), mobility, dopant diffusion, and trap generation. ALD TiN results in a thicker EOT than CVD TiN due to its inherent purging cycle and higher process temperature, but it has a stronger resistance to dopant diffusion. The ALD TiN process also provides better interfacial characteristics, thus better device performance.

Study on off‐state breakdown in AlGaN/GaN HEMTs

We have studied the mechanism of off-state breakdown in AlGaN/GaN high electron mobility transistors (HEMTs). The off-state breakdown voltage (BVoff) had a positive temperature coefficient of 0.12 V/K. BVoff was represented by a monotonous decreasing function of gate leakage current (Ileak), which was analytically derived from the impact ionization coefficient. Our results suggest that off-state breakdown in AlGaN/GaN HEMTs originated from impact ionization in the channel, which was caused by the gate leakage current. BVoff increased with decreasing Ileak by a plasma surface treatment before gate metal deposition. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Impact of metal/oxide interface on DC and RF performance of depletion-mode GaAs MOSFET employing MBE grown Ga 2O 3(Gd 2O 3) as gate dielectric

Employing Ga 2O 3(Gd 2O 3) as gate dielectric and Si-doped GaAs as conducting channel, depletion-mode GaAs MOSFETs were fabricated. DC I– V and transfer curves show no pinch-off and drain current hysteresis. Etching a thin layer from the top of Ga 2O 3(Gd 2O 3) in the gate region before gate metal deposition leads to full pinch-off and significantly reduces the drain current hysteresis. This process may remove the contaminated Ga 2O 3(Gd 2O 3) due to exposure to chemicals and prior processes, and thus results in a clean gate metal to oxide interface. The clean gate metal to Ga 2O 3(Gd 2O 3) interface also leads to higher DC transconductance, higher unity current gain cut-off frequency as well as higher unity power gain cut-off frequency as compared with GaAs MOSFET devices with a contaminated metal/oxide interface at the gate.

Large Gate Leakage Current in AlGaN/GaN High Electron Mobility Transistors

A large gate leakage current in AlGaN/GaN high electron mobility transistors (HEMTs) was observed. Temperature dependence of Ig-Vg characteristics revealed that tunneling current is dominant in the leakage current. By introducing ECR plasma treatment before the gate metal deposition, the gate leakage current was reduced by two to three orders of magnitude.

Temperature dependence of the “0.7” 2e 2/h quasi-plateau in strongly confined quantum point contacts

New results are presented of the “0.7” (2e 2/h) quasi-plateau of strongly confined point contacts. The strong confinement is obtained by combining shallow etching with metal gate deposition on GaAs/GaAlAs heterostructures. The resulting subband separations are up to 20 meV, and consequently, the quantized conductance is observed up to 30 K, an order of magnitude higher than in conventional split gate devices. Pronounced quasi-plateaus are observed at the lowest conductance steps from 1 to 30 K, where all structures are smeared out thermally. The deviation of the conductance from ideal integer quantization exhibits an activated behavior as a function of temperature with a density-dependent activation temperature around of 2 K. Our results are analyzed in terms of a model involving scattering against plasmons in the constriction.

Enhancement-mode high electron mobility transistors (E-HEMTs) lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 /spl mu/m. A maximum extrinsic transconductance (g/sub mext/) of 701 mS/mm and a threshold voltage (V/sub T/) of 167 mV was measured for 0.3 /spl mu/m gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f/sub t/) of 116 GHz was measured as well as a maximum frequency of oscillation (f/sub max/) of 229 GHz for 0.3 /spl mu/m gate-length E-HEMTs.

Fabrication of Y-gate, submicron gate length GaAs metal–semiconductor field effect transistors

0.1 μm Y-shape metal contacts for use as gates on GaAs metal–semiconductor field effect transistors (MESFETs) are produced using a novel SiNx deposition over features 1–2 μm wide, with subsequent etchback and gate metal deposition. Excellent across-wafer uniformity (≤10%) on 3 in. φ substrates is achieved, yielding a simple technique for extending the resolution of conventional optical lithography tools. One of the key features in this method is the need to have an initial negative resist profile. The SiNx is deposited at low temperature (50 °C) by plasma-enhanced chemical vapor deposition in order to avoid distortion of the resist, and exhibits conformal coverage over the initial resist openings. Submicron gate GaAs MESFETs fabricated by this technique have extrinsic transconductance, gm, value of ∼225 mS mm−1 at −0.5 V gate bias, and have comparable performance to devices fabricated using electron-beam lithography to produce a more conventional T-shape gate.

Fabrication of a gated gallium arsenide heterostructure resonant tunneling diode

Techniques used to fabricate a gated resonant tunneling diode (GRTD) are presented. Molecular-beam epitaxy (MBE), image reversal contact photolithography, liftoff metallization, anisotropic reactive ion etching, isotropic liquid etching, and a resulting self-aligned gate metal deposition technique were used to realize this effort. The physical sizes of the fabricated GRTDs were 2, 4, and 6 μm in diameter. The electrical size of the channel within the vertical resonant tunneling diode, however, was controlled by a simple, self-aligned rectifying electrode at the well region. Arrays of devices were fabricated to enhance detection while retaining small geometries. The results from these first devices indicate that an in situ transition from a two-dimensional resonant tunneling diode (RTD) to a zero-dimensional quantum dot is feasible using this design. Improvements in the design are realizable from straightforward modifications in the MBE material.

Total-dose effects of gamma-ray irradiation on CMOS/SIMOX devices : Terukazu Ohno, Katsutoshi Izumi, Masakazu Shimaya and Noboru Shiono. IEEE Circuits Devices Mag., 21 (November 1987)

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO2 gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO2 devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO2 system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.