Metal-ferroelectric-semiconductor Field Effect Transistor Research Articles

Kr-Plasma Sputtering for Pt Gate Electrode Deposition on MFSFET with 5 nm-Thick Ferroelectric Nondoped HfO<sub>2</sub> Gate Insulator for Analog Memory Application

In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

Implementation of low‐power, non‐volatile latch utilising ferroelectric transistor

The implementation of a non-volatile latch circuit developed with a metal–ferroelectric–semiconductor field-effect transistor is presented. The circuit contains two inverter stages in order to create and rectify the desired waveform. The hysteresis properties of the ferroelectric transistor allow it to retain a polarisation state after an applied voltage at the gate is removed. This circuit has reduced power requirements because a constant power supply is not needed at all times; instead, a voltage is only needed at the gate of the ferroelectric transistor when storing a value, and the other components only need a power supply when reading the stored value from the circuit. The circuit is less complex than similar non-volatile latches because only a single ferroelectric transistor is used and fewer overall transistors may be used. It also has the advantage of being radiation-hardened for space applications.

Characteristics of a Three-Transistor DRAM Circuit Utilizing a Ferroelectric Transistor

Dynamic random-access memory (DRAM) cells offer advantages over static random-access memory (SRAM) cells due to their reduced size and relaxed constraints on device sizing ratios. In this paper, the usage of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a three-transistor dynamic random-access memory (DRAM) cell is examined, in order to determine the effects caused by its hysteresis properties. Combinations of metal-oxide-semiconductor field effect transistors (MOSFETs) and MFSFETs are explored, along with implementations consisting only of MFSFETs. The effects seen in these circuit configurations will be compared to configurations using only MOSFETs. Experimental data will be presented, showing the effect of varying parameters of the devices and circuit, such as channel length and width, input voltage waveforms, load devices, and capacitance. Particularly, attention will be given to the application of waveforms containing negative voltages to the gates of the transistors.

Mathematical Models of the Common-Source and Common-Gate Amplifiers Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed in this paper. The models are compared against data collected with MFSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth.

Extended Characterization of the Common-Source and Common-Gate Amplifiers Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and additional device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation of load, quiescent point, or input signal on each circuit are shown. Advantages and applications of the MFSFET and the circuit performance are discussed.

Empirical Data of the Metal-Ferroelectric-Semiconductor Field Effect Transistor Polarization and Channel Resistance for Timing and Retention Analysis

In this paper, empirical data describing the channel resistance and polarization of several metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) is presented. Various channel length and width transistors were used to describe the channel resistance under various biasing conditions and in both positive and negative polarization states. The presented results and analysis provide insight into the switching speed between polarization states as well as the timing and retention constraints for a given set of device dimensions. This is of particular value when considering circuit designs that utilize MFSFETs, especially digital memory circuits.

Expanded Characterization of the Common-Drain Amplifier Using Metal-Ferroelectric-Semiconductor Field Effect Transistors

Data is presented in this paper that was obtained using a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a common-drain amplifier configuration. The empirical data shown has been collected using larger drain voltages than previously seen, which helps to further understand and characterize the interesting operation of this amplifier circuit. The effects of varying different parameters such as load resistance, poling voltage, and input voltages of the amplifier circuit are examined. Differences between the MFSFET and MOSFET common-drain amplifier configurations are explored in-depth.

A Mathematical Model for the Common-Drain Amplifier Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

This paper presents a new mathematical model created for the common-drain amplifier using metal-ferroelectric-semiconductor field effect transistors (MFSFET). The model developed in this paper is based upon empirical data collected through experimentation with the common-drain amplifier while using a MFSFET. Several parameters are considered when calculating the output voltage, such as varying gate capacitance, input voltage, quiescent point, and power supply voltages. A comparison between collected and modeled data is presented as verification of the model's performance when applied to the common-drain configuration.

Transfer characteristics in a GaN MFSFET: comparison with a conventional GaN MOSFET

Based on the Miller model, we develop an analytical model for the GaN-based metal–ferroelectric–semiconductor field-effect transistors (MFSFETs). In this article, we investigate the effects of ferroelectric film on the maximum drain current, transconductance and memory window of GaN MFSFET at the different hierarchical thickness values of 10, 30, 50, 100, 200 and 300 nm, as well as the polarisation influence. The results indicate that the thickness of ferroelectric film is one of the critical parameters, and certain trade-off should be made for various potential applications. Moreover, the advantages of GaN MFSFET are also investigated in detail, compared with the conventional GaN metal–oxide–semiconductor field-effect transistor under the conditions of similar design. Our results of simulation shows that GaN MFSFETs hold the numerous advantages in electrical characteristics, such as the maximal drain current reaching 69 mA, and the threshold voltage and the subthreshold slope as low as 1.5 V and 58 mV/decade, respectively. In general, these theoretical predictions not only indicate that GaN MFSFET devices have wide applicational perspectives, but also they provide some important references to the empirical research and the design of new electron devices in the future.

Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFS-FET) for 1T-type FRAM Based on Polyvinylidene Fluoride (PVDF) Thin Film

The metal-ferroelectric-semiconductor field effect transistor (MFSFET) was fabricated using polyvinylidene fluoride (PVDF) thin film as a ferroelectric layer. PVDF thin films of 4 and 6 wt% were spin-coated on Si(100) wafers. Ferroelectric hysteretic curves inducing a counterclockwise loop, which means that the deposited PVDF films were crystallized with ferroelectric β phase, was exhibited in the drain current–gate voltage (I D –V G ) characteristics of MFSFET. The memory window widths of the MFSFET were more than 1.6 V. The MFSFET that operates with the PVDF thin film used as a gate dielectric material is shown in the drain current–drain voltage (I D –V D ) characteristics. The MFSFET using PVDF as ferroelectric layer has promising potential for use in low-voltage operable one transistor (1T) type ferroelectric random access memories (FeRAM) using organic material.

Fabrication and Electrical Characteristics of Metal–Ferroelectric–Semiconductor Field Effect Transistor Based on Poly(vinylidene fluoride)

We fabricated the metal–ferroelectric–semiconductor field effect transistor (MFSFET) using poly(vinylidene fluoride) (PVDF) thin film as a ferroelectric layer. PVDF thin films were prepared by spin-coating PVDF solutions of 2–6 wt % on Si(100) wafers with source and drain diffusion regions. The drain current–gate voltage (ID–VG) characteristics of MFSFET exhibited ferroelectric hysteretic curves inducing a counterclockwise loop similar to that of other ferroelectric materials. It seems that the deposited PVDF films were crystallized with the ferroelectric β phase. The memory window widths of the MFSFET were more than 1.0 V. The drain current–drain voltage (ID–VD) characteristics show that the MFSFET operates with the PVDF thin film used as a gate dielectric material. The MFSFET using PVDF as ferroelectric layer has promising potential for use in low-voltage operable one-transistor (1T)-type ferroelectric random access memories (FeRAMs) using organic material.

METAL-FERROELECTRIC-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR NAND GATE SWITCHING TIME ANALYSIS

ABSTRACT Previous research investigated the modeling of a NAND gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

The modeling of a NAND gate constructed of Metal-Ferroelectric-Semiconductor Field Effect Transistors (MFSFETs) has been investigated. Initially, an inverter circuit was modeled using a n-channel MFSFET with positive polarization for a standard CMOS inverter n-channel transistor and a n-channel MFSFET with negative polarization for the standard CMOS inverter p-channel transistor. The MFSFETs were simulated by using a previously developed MFSFET model which utilized a partitioned ferroelectric layer. Then a 2-input NAND gate was modeled similar to the inverter gate. The data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Fabrication and Characterization of Metal/Ferroelectric/Semiconductor Field Effect Transistor with the Ag/Bi4Ti3O12/p-Si(100) Structure

Metal–ferroelectric–semiconductor field-effect-transistors (MFS-FETs) with the Ag/Bi4Ti3O12/p-Si (100) structures were fabricated. The Ids–Vg hysteresis curve of the FET shows the counter-clockwise direction, which demonstrates the charge of channel conductivity due to the ferroelectric polarization of Bi4Ti3O12 and the memory window with a gate voltage of ±6 V was 1.2 V. The current ratio of Ids(on) to Ids(off) was over two orders in magnitude at zero gate voltage which indicates the MFS-FET can be used in nondestructive readout (NDRO) applications.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated. A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the “1” and “0” logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the “1” and “0” logic states for a long period of time.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor Modeling Using a Partitioned Ferroelectric Layer

A combination empirical/theoretical n-channel metal-ferroelectric-semiconductor field-effect transistor (MFSFET) model is developed. The model is based on a partition concept where the MFSFET ferroelectric material is segmented, allowing each individual segment to maintain an independent polarization solution as a function of applied electric field history. Modifications are made to pertinent classical metal-oxide-semiconductor field-effect transistor device equations to include the presence of ferroelectric dipole polarization charge. The model's usage of ferroelectric polarization is numerical in nature, allowing both analytic and non-analytic ferroelectric polarization models to be used. Simulation results showing the effects of the ferroelectric model parameters on MFSFET drain current are presented, including active and remnant saturated hysteresis and retention.

Ferroelectric-gate field effect transistors using Nd 2Ti 2O 7/Y 2O 3/Si structures

Ferroelectric field effect devices offer the possibility of non-volatile active memory elements. In the metal–ferroelectric–semiconductor field effect transistor, it is important for a ferroelectric material to have a low dielectric constant to enable the application of sufficient electric field to a ferroelectric film. In this work, we report the fabrication and characterization of a ferroelectric-gate field effect transistor using Nd 2Ti 2O 7(NTO)/Y 2O 3/Si structures. The crystalline property of the film as a function of annealing temperature was characterized by X-ray diffraction. C– V characteristics were measured to investigate the ferroelectric memory effects at 1 MHz with a bias sweep rate of 0.18 V/s. As a result, the memory windows were in the range of 0.98–3.31 V when the applied voltage varied from 3 to 9 V. Specifically, we confirmed the ferroelectricity of crystallized NTO films.

Characteristics of LiNbO3 memory capacitors fabricated using a low thermal budget process

We investigated LiNbO3 metal ferroelectric semiconductor (MFS) capacitors because of the following advantages: a low interface trap density, a low interaction with Si substrate, and a large remanent polarization. Ferroelectric LiNbO3 thin films were grown directly on p-type Si(100) substrates for metal ferroelectric semiconductor field effect transistor (MFSFET) applications. Low temperature film growth and post rapid thermal anneal (RTA) treatments improved the leakage current of films while keeping other properties almost the same as high substrate temperature grown samples. We reduced the leakage current density of LiNbO3 films from 10−5 A/cm2 to 10−7 A/cm2 with RTA treatment. LiNbO3 MFS capacitors exhibited a breakdown electric field of greater than 500 kV/cm. RTA treatment above 600°C converted LiNbO3 films from amorphous to polycrystalline states with (012), (015), (022), and (023) planes. The polycrystalline LiNbO3 MFS capacitors illustrated the ferroelectric switching characteristics with a memory window ranging from 0.6 to 1.9 V. We obtained a remanent polarization of 2.74 μC/cm2 and a coercive field of 170 kV/cm using the LiNbO3 MFS capacitors.

A drain current data capture system for metal-ferroelectric-semiconductor field-effect transistors

A data capture system was developed to measure drain current as a function of gate-to-source voltage and drain-to-source voltage for Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs). Data from active hysteresis, remanent hysteresis, and retention tests were collected. The system consisted of an IBM-compatible PC equipped with an analog data acquisition system and a General Purpose Interface Bus (GPIB) controller, a voltage pulse generator, a custom MFSFET evaluation circuit, dual power supplies, and several custom software modules. Software modules were written to collect drain current data from all of the MFSFETs simultaneously, while controlling drain voltage, pulse width, and gate voltage pulse waveform sequencing remotely. System capabilities were: drain voltage from 0 to 10 volts, gate voltage from − 16 to + 16 volts, and pulse width from 1 μsec to 0.999 sec. The system allowed a high degree of flexibility and customization with regard to system inputs and facilitated completely automated testing.

Processing and characterization of LiNbO3 thin film for metal Ferroelectric Semiconductor field effect transistor (MFSFET) application

LiNbO3 thin films were deposited on P-Si(111) substrates. C-axis (006) oriented films were fabricated with RF magnetron sputtering and (012) oriented films were achieved by metal organic decomposition (MOD). High frequency C-V measurement showed a clockwise rotation hysteresis curve, which corresponded to the ferroelectric switching. A polarization vs. voltage hysteresis curve of a Metal-Ferroelectric-Semiconductor (MFS) capacitor was measured with a modified Sawyer-Tower circuit. Remnant polarization as high as 65μC/cm2 was found from sputtering deposited sample.