Characteristics of a Three-Transistor DRAM Circuit Utilizing a Ferroelectric Transistor

Abstract

Dynamic random-access memory (DRAM) cells offer advantages over static random-access memory (SRAM) cells due to their reduced size and relaxed constraints on device sizing ratios. In this paper, the usage of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) in a three-transistor dynamic random-access memory (DRAM) cell is examined, in order to determine the effects caused by its hysteresis properties. Combinations of metal-oxide-semiconductor field effect transistors (MOSFETs) and MFSFETs are explored, along with implementations consisting only of MFSFETs. The effects seen in these circuit configurations will be compared to configurations using only MOSFETs. Experimental data will be presented, showing the effect of varying parameters of the devices and circuit, such as channel length and width, input voltage waveforms, load devices, and capacitance. Particularly, attention will be given to the application of waveforms containing negative voltages to the gates of the transistors.