Metal-ferroelectric-insulator-semiconductor Research Articles

Enhancing ferroelectricity in HfAlOx-based ferroelectric tunnel junctions: A comparative study of MFS and MFIS structures with ultrathin interfacial layers

This study explores the potential advantages of metal–ferroelectric–insulator–semiconductor (MFIS) structures compared with established metal–ferroelectric–semiconductor (MFS) and metal–ferroelectric–metal structures in the context of nonvolatile memory devices. Despite the superior performance of MFS structures in terms of electric field maintenance, switching speed, and power consumption, the presence of interface-related issues between the ferroelectric material and the semiconductor may degrade device performance. We propose an MFIS structure incorporating ultrathin interfacial layers (ILs) of SiO2, HfO2, and ZrO2 to address these issues. These insulator layers enhance device endurance by reducing physical stress and trap density at the interface, thereby improving electrical performance and long-term stability. Moreover, the presence of an IL reduces charge leakage between the ferroelectric layer and semiconductor, contributing to the resolution of the sneak path current problem. An additional feature of MFIS devices is their self-rectifying behavior, simplifying circuit design and manufacturing processes by eliminating the need for an external rectification circuit, consequently reducing costs. Through a series of experiments, this study evaluates the performance of the MFIS structure, investigates the ferroelectric properties of HfAlOx-based FTJs, and examines the conduction mechanism of the MFIS structure. By comparing the o-phase of MFS, SiO2, HfO2, and ZrO2 devices via grazing incidence X-ray diffraction (GIXRD) and using the positive-up-negative-down method to extract polarization and coercive voltage, we provide a comprehensive investigation of the impact of ultrathin ILs on ferroelectric properties. This research aims to offer valuable insights into the advancement of memory device technologies, presenting the MFIS structure as a promising platform for next-generation memory technologies. Further sections will elaborate on the experimental setup, methodology, and detailed study findings.

Artificial neural network models for metal-ferroelectric-insulator-semiconductor ferroelectric tunnel junction memristor

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure ferroelectric tunnel junction (FTJ) memristor becomes one of the most promising candidates for next-generation memories. Two numerical simulation methods have been developed and analyzed previously to calculate the tunneling current in the MFIS-FTJ, one by using the Wentzel–Kramers–Brillouin (WKB) method with the band profile obtained from Poisson's equation, the other by self-consistently solving Poisson's equation and the drift-diffusion transport equations with a tunneling-induced carrier generation rate. However, numerical methods can be computationally expensive, especially for device design with various parameters. In this work, an artificial neural network (ANN) model that can predict the device performance is proposed, the model can reduce computational cost while maintaining good accuracy. In addition, to further investigate the applicable conditions of the two simulation methods mentioned above, we also develop an ANN model to predict the relative differences between the two methods' results under different conditions, and the prediction results show good agreement with numerical results.

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications

This paper presents the detailed analysis of n-channel Negative Capacitance Cylindrical Gate All Around Field Effect Transistor (NC-CGAAFET) of class Metal-Ferroelectric-Insulator Semiconductor (MFIS) at 2 nm technology node and its comparison with CGAAFET (Cylindrical Gate All Around Field Effect Transistor). NC-CGAAFET shows better performance in terms of ION, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), and ION/IOFF when compared to CGAAFET. Further, NC-CGAAFET is analyzed at different values of ferroelectric layer thickness (TFE), along with different values of spacer dielectric constant (K), spacer length (LSP) and nanowire diameter (DNW) and found that SS goes below Boltzmann's limit (60 mV/dec) and further decreases with increasing TFE. Also observed that Negative-DIBL increases as TFE increases. In addition to this, the device is optimized for NDR (Negative Differential Resistance) free operation, to be applicable for both analog and digital applications, by varying TFE. The optimized NDR free NC-CGAAFET offers SS of 59.33 mV/dec, DIBL of 13.91 mV/V, and the ION/IOFF ratio of 3.28x higher than conventional CGAAFET by operating at low power supply (VDD ∼ 0.65V).

Analog Synaptic Devices Based on IGZO Thin‐Film Transistors with a Metal–Ferroelectric–Metal–Insulator–Semiconductor Structure for High‐Performance Neuromorphic Systems

A ferroelectric thin‐film transistor (FeTFT)‐based synaptic device with an indium–gallium–zinc oxide (IGZO) channel and a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure is reported. The fabricated FeTFT exhibits a highly linear conductance response (|α| = 0.21) with a large dynamic range (Gmax/Gmin ≈ 53.2), although identical program pulses are applied to the device. In addition, because the inner metal layer of the FeTFTs has an MFMIS structure, the electric field is uniformly applied to the entire IGZO channel, which reduces the cycle‐to‐cycle variation (σ = 0.47%) in the conductance responses. In the system simulation with the measured synaptic characteristics, the high classification accuracy of ≈97.0% is achieved in the MNIST image set, verifying the feasibility of FeTFT‐based neuromorphic systems.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

Hydrogen Bonding-Assisted Complete Ferroelectric β-Phase Conversion in Poly(vinylidene fluoride) Thin Films: Exhibiting an Excellent Memory Window and Long Retention.

Organic nonvolatile memory with low power consumption is a critical research demand for next-generation memory applications. Ferroelectric switching characteristics of poly(vinylidene fluoride) (PVDF) thin films modified with a trace amount of hydrated Cu salt (CuCl2·2H2O) are explored in the present study. Herein, a Cu salt-mediated PVDF (Cu/PVDF) thin film with preferential edge-on β-crystallites is fabricated through the orientation-controlled spin coating (OCSC) technique. This work proposes a convenient and effective approach to produce edge-on-oriented electroactive PVDF thin films with a high degree of polar β-phase, so as to realize the favorable switching under low operating voltages. Herein, chemically modified PVDF is anticipated to form a complex intermediate, which attains its stability by undergoing favorable hydrogen bonding that reorients the C-C structure of PVDF to obtain the β-conformation. Such information is verified by X-ray photoelectron spectroscopy (XPS). Grazing incidence Fourier transform infrared (GI-FTIR) spectroscopy revealed that the Cu salt incorporated into the PVDF matrix favored the formation of the electroactive β-phase with edge-on crystallite lamellae. Consequently, the Cu/PVDF thin film demonstrates a good contrast between electric field-assisted written and erased data bits in the piezoresponse force microscopy (PFM) phase image. Furthermore, to obtain the ferroelectric memory window, a metal-ferroelectric-insulator-semiconductor (MFIS) diode with Cu/PVDF as a ferroelectric layer has been fabricated. The capacitance-voltage (C-V) characteristic of the MFIS diode exhibits a memory window of 12 V with a long-term retention behavior (∼longer than 7 days). In a nutshell, we tried to represent a clear understanding of the interfacial interactions of the Cu salt with PVDF, which favor the edge-on formation that results in the promising low-voltage ferroelectric switching and excellent retention response, where any additional electrical poling and/or external stretching is completely possible to be ruled out, thus offering a new prospect for the evolution of devices with long-lasting nonvolatile memories.

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Modeling of Ionizing Radiation Effects for Negative Capacitance Field-Effect Transistors

A theoretical model for simulating ionizing radiation effects on negative capacitance field-effect transistors (NCFETs) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure was established. Based on the model, the effects of total ionizing dose (TID) and dose rate on the surface potential, ferroelectric capacitance, voltage amplification factor, and transfer characteristics of NCFETs were investigated. The simulation results demonstrated that, with the increase in total dose, the curves of surface potential versus gate voltage and driving current versus gate voltage shift left significantly, resulting in the point of voltage amplification shifting left. Meanwhile, with the increase in dose rate, the amplitude of both the surface potential and driving current decreases slightly. Meanwhile, the derived result indicated that relatively thin ferroelectric thickness can effectively reduce the effect of TID. It is expected that this model can be helpful for analyzing the radiation effects of NCFETs.

Low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors with metal–ferroelectric–metal–insulator–semiconductor structure

We investigate the low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors (FeTFTs) with a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. MFMIS FeTFTs are fabricated with different metal-to-FE area ratios (AM/AF's). It is revealed that the noise generation mechanism differs depending on the operation region [low and high drain current (ID) regions] and AM/AF. Excess noise in the low ID region is observed in the MFMIS FeTFTs with AM/AF's of 4 and 6 due to carrier mobility fluctuations. In the high ID region, the carrier number fluctuation generates the 1/f noise of the devices regardless of the AM/AF.

Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance

Negative Capacitance Field Effect Transistors (NCFETs) offer the possibility of enhancing channel length scalability, with a key challenge being to ensure hysteresis and Negative Differential Resistance (NDR) free behavior. In this context, through TCAD-based simulations, for a symmetric Double-gate Silicon-on-Insulator (DG-SOI) baseline architecture with a Metal–Ferroelectric–Insulator–Semiconductor (MFIS) configuration, we first examine the root cause of NDR as being the FE layer with a small number of strongly coupled domains, which allows the drain to lower the surface potential (ΨSs) and internal gate voltage (Vint) on the source side. With this understanding of NDR, the inclusion of a paraelectric (PE) layer on the drain side of the gate stack, by splitting the stack into two halves laterally, while keeping the thickness of the stack unchanged, minimizes the drain’s influence on the source-sided electrostatics. This results in the mitigation of NDR effects along with superior analog performance parameters, thus making these FE–PE gate stack-based NCFET devices suitable for analog circuit applications.

Long term retention in δ‐PVDF thin film prepared by rapid ice quenching technique

AbstractFerroelectric δ‐phase comprising polyvinylidene fluoride (δ‐PVDF) thin films are prepared via spin‐coating followed by high‐temperature annealing and rapid ice quenching, where, the requirement of a high electric field (~MV/m) is circumvented. Herein, ferroelectric responses, that is, “write,” “erase,” and “read” pulses on as prepared δ‐PVDF thin film, have been demonstrated through piezoresponse force microscopy (PFM). A metal‐ferroelectric‐insulator–semiconductor (MFIS) diode containing δ‐PVDF has shown a capacitance–voltage (C–V) hysteresis with a notable memory window of 7.5 V up to a temperature of 140°C, overcoming lower fatigue temperatures, limited by Curie transition in co‐polymer P(VDF‐TrFE). A very stable polarization state is reflected by a holding period of a capacitance state of 10 h, where only a 5% loss of its initial value is noticed. The excellent ferroelectric response and retention behavior of the δ‐PVDF thin film may open up new opportunities in the field of high‐endurance non‐volatile memories.

Large ferro–pyro–phototronic effect in 0.5Ba(Zr0.2Ti0.8)O3–0.5(Ba0.7Ca0.3)TiO3 thin films integrated on silicon for photodetection

AbstractCoupling together the ferroelectric, pyroelectric, and photovoltaic characteristics within a single material is a novel way to improve the performance of photodetectors. In this work, we take advantage of the triple multifunctionality shown by 0.5Ba(Zr0.2Ti0.8)O3–0.5(Ba0.7Ca0.3)TiO3 (BCZT), as demonstrated in an Al/Si/SiOx/BCZT/ITO thin‐film device. The Si/SiOx acts as an n‐type layer to form a metal–ferroelectric–insulator–semiconductor heterostructure with the BCZT, and with Al and ITO as electrodes. The photo‐response of the device, with excitation from a violet laser (405 nm wavelength), is carefully investigated, and it is shown that the photodetector performance is invariant with the chopper frequency owing to the pyro‐phototronic effect, which corresponds to the coupling together of the pyroelectric and photovoltaic responses. However, the photodetector performance was significantly better than that of the devices operating based only on the pyro‐phototronic effect by a factor of 4, due to the presence of ferroelectricity in the system. Thus, after a poling voltage of −15 V, for a laser power density of 230 mW/cm2 and at a chopper frequency of 400 Hz, optimized responsivity, detectivity, and sensitivity values of 13.1 mA/W, 1.7 × 1010 Jones, and 26.9, respectively, are achieved. Furthermore, ultrafast rise and fall times of 2.4 and 1.5 µs, respectively, are obtained, which are 35,000 and 36,000 times faster rise and fall responses, respectively, than previous reports of devices with the ferro–pyro–phototronic effect. This is understood based on the much faster ferroelectric switching in ferroelectric thin films owing to the predominant 180° domains in a single direction out of plane.

Theoretical Study of Carrier Transport in Metal–Ferroelectric–Insulator–Semiconductor Ferroelectric Tunnel Junction Memristor

Ferroelectric tunnel junction (FTJ) based on the metal–ferroelectric–insulator–semiconductor (MFIS) stacks shows great potential in neuromorphic and in-memory computing. Tunneling current in the MFIS-FTJ can be calculated by the Wentzel–Kramers–Brillouin (WKB) method with the band profile solved from Poisson’s equation or by self-consistently solving Poisson’s equation and the drift-diffusion transport equations with a tunneling-induced carrier generation rate. The carrier redistribution in the semiconductor is neglected in the former method, which reduces the complexity and saves the computational cost but may or may not lead to significant errors. In this article, a comprehensive study of the two simulation methods mentioned above is performed to investigate their applicable conditions and balance the accuracy and computational cost. The current densities of the MFIS-FTJs with different material parameters, including the barrier width, barrier height, carrier mobility, and polarization charge density simulated by the two methods, are compared and analyzed. As the voltage drop across the semiconductor cannot be neglected, method II is required to take the carrier transport in the semiconductor into account and method I is not accurate; otherwise, method I is more suitable due to its low computational cost without loss of accuracy.

(Invited, Digital Presentation) Super-Nernstian Isfet Combining Two-Dimensional WSe2/MoS2 Heterostructure with Negative Capacitance

Ion-sensitive field-effect transistors (ISFETs) are quite popular as compact, low-cost biosensors with fast response time and label-free detection1. They can be used as pH sensors or functionalized for complex biomolecule detection. The voltage sensitivity (Sv) in classical ISFETs is fundamentally limited to 59 mV/pH (Nernst limit). Surpassing the Nernst limit requires complex device architectures or novel transport phenomena. Sensitivity beyond the Nernst limit can be achieved using specific device architectures such as dual gate ISFETs2, negative capacitance ISFETs (NC-ISFET)3, tunnel ISFETs4, etc. Compatible architectures can be combined for further enhancements in sensitivity.First, we experimentally demonstrate a super-Nernstian hetero-ISFET that uses 2-D WSe2/MoS2 heterostructure in a double-gated configuration5. The schematic of the device structure is shown in Fig. 1(a) along with its dimensions. The fluid gate to the pH solution is biased at VFG = 0 V and the voltage sensitivity (SV) is extracted by applying bias to the back-gate (VBG). Fig. 1(b) shows the variation of drain current for change in VBG at different pH. The voltage sensitivity is also included in the same graph. The device uses charge screening due to the interface traps and inversion charges at the hetero-interface to modulate the back-gate transconductance (gmb), thereby allowing super sensitivity.Further enhancement in sensitivity is explored using technology computer-aided (TCAD) device simulator tool (Silvaco ATLAS) by integrating with different device architectures. First we model the baseline hetero-ISFET. The 2-D materials were modeled using their material parameters and 3-D equivalents of their density of states. Amorphous hafnium oxide (HfO2) was used as the dielectric. The mobile ions in the electrolyte were modeled as charge carriers in an intrinsic semiconductor, with its effective density of states varying as a function of pH. The simulation model was calibrated with the experimental device (at pH = 7), as shown in Fig. 2(a). The transfer characteristics of the back-gate at different pH and fixed VFG (= 0 V) for the simulated device is shown in Fig. 2(b). We note that the sensitivity from simulations is lower than the experimental device. This is likely due to non-ideal and 2-D material specific factors which are not accounted in simulations. Nevertheless, the simulated device also shows super-Nernstian sensitivity (Fig. 2(b), right axis), validating the model. Hence, the calibrated TCAD model is used as the baseline for further studies.Next, an NC-FE layer (aluminum-doped HfO2) was added to the top fluid-gate stack6. We have used a ferroelectric-metal-insulator-semiconductor (FMIS) stack for the proposed NC-hetero-ISFET. Fig. 3(a) shows the new top-gate stack with the FMI layer, which replaces the top-gate stack in the earlier schematic. The fluid-gate charge (QFG), and drain current (ID) as a function of VFG (VBG = 0 V), were obtained from the TCAD simulations. The 1-D Landau–Khalatnikov (L-K) equations were used to model the voltage across the FE layer (VFE = 2αQFG+4βQ3 FG = V' FG - Vint; where V' FG is the newly computed fluid-gate bias and Vint is the internal node voltage)7. The calculated Vint (for fixed V' FG) is coupled back into the ATLAS simulator to extract voltage sensitivity (SV) by sweeping VBG at different pH values.The fluid-gate transfer curve of the proposed NC-hetero-ISFET, in Fig. 3(b), clearly shows a steeper sub-threshold slope and higher ON current than the baseline device. The corresponding FE layer parameters are shown in Table 1. These improved fluid-gate characteristics contribute to an increased voltage-sensitivity (SV) when VBG is applied. The transfer characteristic (ID v/s VBG, at fixed V' FG) of the NC-hetero-ISFET at different pH values is shown in Fig. 3(c), along with the voltage sensitivity. Further, in Fig. 3(d), we compare the peak SV obtained at different V' FG. There is an improvement in voltage sensitivity (as much as ~ 100 mV/pH) over the baseline device when NC is introduced. The results pave the way for highly sensitive super-Nernstian ISFETs by combining 2-D heterostructure with NC effect.

Improved remnant polarization of Zr-doped HfO2 ferroelectric film by CF4/O2 plasma passivation

In this work, the impact of fluorine (CF4) and oxygen (O2) plasma passivation on HfZrOx (HZO) based ferroelectric capacitor was investigated. By the fluorine passivation, the surface trap density and oxygen vacancies in the HZO-based Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were suppressed, resulting in the increased pristine remnant polarization (2Pr). The pristine value (2Pr) of baseline samples annealed at 500 °C and 600 °C were 11.4 µC/cm2 and 24.4 µC/cm2, respectively. However, with the F–passivation, the 2Pr values were increased to 30.8 µC/cm2 and 48.2 µC/cm2 for 500 °C and 600 °C, respectively. The amount of surface defects and oxygen vacancies are quantitatively confirmed by the conductance method and XPS analysis. However, due to the incorporation of fluorine atoms into the ferroelectric–insulator films, undesirable degradation on endurance characteristics were observed.

FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs

Given the short-channel effect immunity of junction-less architectures, further improvement in device performance can be obtained by using a Negative Capacitance based gate stack over such baseline devices. By benchmarking the baseline device, which is a partially Junction-less MOSFET structure, essentially a combination of the Junction-less and Bulk MOSFET device architectures, with experimental data, we then investigate the relative effect of the inclusion of a Ferroelectric (FE) material and Ferroelectric-Paraelectric (FE-PE) stack, respectively, on the existing dielectric (DE) gate stack of the baseline device, resembling a more practical Metal-Ferroelectric-Insulator-Semiconductor (MFIS) NCFET (Negative Capacitance Field Effect Transistor) structure. By ensuring Hysteresis-free transfer characteristics, positive output conductance and Sub-threshold Slope/Threshold Voltage invariability to drain voltage, the FE layer thickness and power supply voltage (maximum drain–source voltage) of the FE-DE and FE-PE-DE gate stacks are determined, which are nearly equivalent capacitively and therefore show similar digital device performance, with the FE-PE-DE gate stack based NCFET showing significantly better analog device performance.

Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack

With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage () that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage (), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics (–) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance (), resulting in improved dc gain () and improved linearity parameters ( and ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.

Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance

Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.

Oxygen‐Scavenging Effects of Added Ti Layer in the TiN Gate of Metal‐Ferroelectric‐Insulator‐Semiconductor Capacitor with Al‐Doped HfO2 Ferroelectric Film

AbstractTi layer inserted in the TiN gate electrode effectively scavenges the oxygen in the low‐k interfacial SiO2 of the metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with the ferroelectric Al‐doped HfO2 (HAO) thin film. The scavenging effect increases remanent polarization (Pr) and reduces coercive voltage (Vc) and capacitance equivalent thickness (CET) of the HAO films, particularly when the MFIS capacitor is annealed at 800 °C. Additionally, frequency dispersion of capacitance characteristics and interface trap density (Dit) calculations reveal that actively‐triggered oxygen‐scavenging effects also reduce defect or trap‐induced degradation. The Ti‐inserted MFIS structure exhibits fatigue‐free endurance and relatively low leakage current characteristics as compared to a structure without the Ti scavenging layer in high annealing temperature conditions required for crystallization of the HAO ferroelectric films.

Improvement in nonvolatile memory operations for metal–ferroelectric–insulator–semiconductor capacitors using HfZrO2 and ZrO2 thin films as ferroelectric and insulator layers

Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were characterized to elucidate the optimum design schemes for the ferroelectric field-effect transistor applications. The Hf1−x Zr x O2 (HZO) thin films (18 nm) were prepared on the SiO2 and ZrO2 insulator layers (ILs) with different film thicknesses. The choice of 10 nm thick ZrO2 IL was found to be an optimum condition to properly balance between the values of electric fields applied to the HZO (E HZO) and ZrO2 (E IL) layers, leading to effective improvement in capacitance coupling ratio and to suppression of charge injection for the MFIS capacitors. Furthermore, the crystalline natures of the crystallized HZO films were also found to be strategically controlled on the ZrO2 ILs, which can additionally enhance the E HZO with reducing the E IL. As consequences, the MFIS capacitors using 10 nm thick ZrO2 IL exhibited the ferroelectric memory window as large as 2.5 V at an application of ±5 V, which corresponds to 2.7 times wider value, compared to that obtained from the device using 2 nm thick SiO2 IL. Long-time memory retention and robust program endurance were also verified for the fabricated MFIS capacitors.