FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs

Abstract

Given the short-channel effect immunity of junction-less architectures, further improvement in device performance can be obtained by using a Negative Capacitance based gate stack over such baseline devices. By benchmarking the baseline device, which is a partially Junction-less MOSFET structure, essentially a combination of the Junction-less and Bulk MOSFET device architectures, with experimental data, we then investigate the relative effect of the inclusion of a Ferroelectric (FE) material and Ferroelectric-Paraelectric (FE-PE) stack, respectively, on the existing dielectric (DE) gate stack of the baseline device, resembling a more practical Metal-Ferroelectric-Insulator-Semiconductor (MFIS) NCFET (Negative Capacitance Field Effect Transistor) structure. By ensuring Hysteresis-free transfer characteristics, positive output conductance and Sub-threshold Slope/Threshold Voltage invariability to drain voltage, the FE layer thickness and power supply voltage (maximum drain–source voltage) of the FE-DE and FE-PE-DE gate stacks are determined, which are nearly equivalent capacitively and therefore show similar digital device performance, with the FE-PE-DE gate stack based NCFET showing significantly better analog device performance.