Metal-ferroelectric-insulator-semiconductor Structure Research Articles

Enhancing ferroelectricity in HfAlOx-based ferroelectric tunnel junctions: A comparative study of MFS and MFIS structures with ultrathin interfacial layers

This study explores the potential advantages of metal–ferroelectric–insulator–semiconductor (MFIS) structures compared with established metal–ferroelectric–semiconductor (MFS) and metal–ferroelectric–metal structures in the context of nonvolatile memory devices. Despite the superior performance of MFS structures in terms of electric field maintenance, switching speed, and power consumption, the presence of interface-related issues between the ferroelectric material and the semiconductor may degrade device performance. We propose an MFIS structure incorporating ultrathin interfacial layers (ILs) of SiO2, HfO2, and ZrO2 to address these issues. These insulator layers enhance device endurance by reducing physical stress and trap density at the interface, thereby improving electrical performance and long-term stability. Moreover, the presence of an IL reduces charge leakage between the ferroelectric layer and semiconductor, contributing to the resolution of the sneak path current problem. An additional feature of MFIS devices is their self-rectifying behavior, simplifying circuit design and manufacturing processes by eliminating the need for an external rectification circuit, consequently reducing costs. Through a series of experiments, this study evaluates the performance of the MFIS structure, investigates the ferroelectric properties of HfAlOx-based FTJs, and examines the conduction mechanism of the MFIS structure. By comparing the o-phase of MFS, SiO2, HfO2, and ZrO2 devices via grazing incidence X-ray diffraction (GIXRD) and using the positive-up-negative-down method to extract polarization and coercive voltage, we provide a comprehensive investigation of the impact of ultrathin ILs on ferroelectric properties. This research aims to offer valuable insights into the advancement of memory device technologies, presenting the MFIS structure as a promising platform for next-generation memory technologies. Further sections will elaborate on the experimental setup, methodology, and detailed study findings.

Oxygen‐Scavenging Effects of Added Ti Layer in the TiN Gate of Metal‐Ferroelectric‐Insulator‐Semiconductor Capacitor with Al‐Doped HfO2 Ferroelectric Film

AbstractTi layer inserted in the TiN gate electrode effectively scavenges the oxygen in the low‐k interfacial SiO2 of the metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with the ferroelectric Al‐doped HfO2 (HAO) thin film. The scavenging effect increases remanent polarization (Pr) and reduces coercive voltage (Vc) and capacitance equivalent thickness (CET) of the HAO films, particularly when the MFIS capacitor is annealed at 800 °C. Additionally, frequency dispersion of capacitance characteristics and interface trap density (Dit) calculations reveal that actively‐triggered oxygen‐scavenging effects also reduce defect or trap‐induced degradation. The Ti‐inserted MFIS structure exhibits fatigue‐free endurance and relatively low leakage current characteristics as compared to a structure without the Ti scavenging layer in high annealing temperature conditions required for crystallization of the HAO ferroelectric films.

Modeling Multigate Negative Capacitance Transistors With Self-Heating Effects

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations.

Channel doping effects in negative capacitance field-effect transistors

The channel doping effects in negative capacitance field-effect transistors (NCFETs) of the metal-ferroelectric-insulator-semiconductor (MFIS) structure are analysed in this work, and an analytical model is developed. The NCFET threshold voltage with channel doping is defined, and a nonmonotonic dependence on the doping concentrations is predicted. A unified charge formulation is developed for the current–voltage characteristics of double gate MFIS structures. Statistical modelling for NCFETs is further developed. Standard deviations of four parameters are extracted, reproducing the distributions of NCFET current–voltage characteristics. Experimental calibrated TCAD simulations validate the analytical model for wide ranges of device parameters, allowing its application to devices and circuits.

Metal (Pt)/ferroelectric (SrBi2Ta2O9)/insulator (La2O3)/semiconductor (Si), MFIS structures for nonvolatile memory applications

Extended data retention is a cardinal impediment for ferroelectric memories and serves a pivotal role for nonvolatile memory applications. Here, nonvolatile Metal–Ferroelectric–Insulator–Semiconductor (MFIS) structures are fabricated by using thin films of Strontium Bismuth Tantalum Oxide (SrBi2Ta2O9) as ferroelectric and high-κ lanthanum oxide (La2O3) as a buffer insulator on p-Si substrates via RF magnetron sputtering. The grazing incidence x-ray diffraction analysis confirms the dominant (111) and (115) ferroelectric perovskite phases of SrBi2Ta2O9 thin films. Albeit, atomic force microscopy surface micrographs revealed highly smooth La2O3 and SBT (SrBi2Ta2O9) thin films with a surface roughness of ∼0.22 ± 0.04 nm and ∼1.05 ± 0.03 nm, respectively. Capacitance–voltage (C–V), capacitance–time (C–T), and current–voltage (I–V) characteristics of Pt/SrBi2Ta2O9/La2O3/Si, MFIS structures, exhibited a high memory window of ∼1.1 V at ±5 V sweep voltage, data retention measured until ∼104 s even on the extrapolation up to 10 years, and a low leakage current density of ∼12.8 μA/cm2 at −1 V and 300 K. Far from it, the probed conduction mechanism is studied for Pt/SrBi2Ta2O9/La2O3/Si MFIS device structures. The optimum nonvolatile memory characteristics are attributed to the high-quality SBT ferroelectric and the buffer layer La2O3/Si interface of the investigated MFIS structure and also assert from the control Pt/SBT/Pt and Pt/La2O3/Si results. Thus, the proposed Pt/SrBi2Ta2O9/La2O3/Si structure is a potential candidate for a gate stack of one-transistor (1T) type Ferroelectric Field-Effect Transistors nonvolatile memory applications.

Ferroelectric field effect transistors: Progress and perspective

Ferroelectric field effect transistors (FeFETs) have attracted attention as next-generation devices as they can serve as a synaptic device for neuromorphic implementation and a one-transistor (1T) for achieving high integration. Since the discovery of hafnium–zirconium oxide (HZO) with high ferroelectricity (even at a thickness of several nanometers) that can be fabricated by a complementary metal–oxide–semiconductor-compatible process, FeFETs have emerged as devices with great potential. In this article, the basic principles of the FeFET and the design strategies for state-of-the-art FeFETs will be discussed. FeFETs using Pb(ZrxTi1−x)O3, polyvinylidene fluoride, HZO, and two-dimensional materials are emphasized. FeFETs, ferroelectric semiconductor field effect transistors, and metal–ferroelectric–insulator–semiconductor structures to which those materials can be applied are introduced, and their exotic performances are investigated. Finally, the limitations of these devices’ current performance and the potential of these materials are presented.

CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications

A low-cost fabrication process of Hf <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) nonvolatile memory (NVM) was proposed and its characteristics were investigated. We successfully fabricated a ferroelectric tunnel junction (FTJ) device with tunable conductance for neural network applications. The proposed FTJ device exhibits excellent performances, such as large conductance ratio of ~40 for a 500-ns pulse and thus satisfied low-power consumption of write pulse (1 fJ per bit) and fast write speed (<500 ns) requirements. Furthermore, we revealed that the metal–ferroelectric–insulator–semiconductor structure had a higher tunneling electroresistance ratio than the metal–ferroelectric–insulator–metal structure. Moreover, the polarization operation of our FTJ devices achieved low-power analog-like conductance transition, multilevel operation, and even endurance characteristics is promising. These results demonstrate that the FTJ has high potential to be an ideal emerging memory for neuromorphic computing. Therefore, HZO-based devices are promising materials in neural network applications for next-generation devices.

Impact of Radiation Effect on Ferroelectric Al-Doped HfO2 Metal-Ferroelectric- Insulator-Semiconductor Structure

The $\gamma $ -ray total dose radiation effects on ferroelectric Al-doped HfO2 (HfAlO) thin films with an n-type Si substrate were studied. The $I$ - $V$ , $P$ - $V$ , $C$ - $V$ and fatigue characteristics of the HfAlO-based Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure were analyzed with the increasing total dose from 0 to 1 Mrad (Si). The remnant polarization ( $P_{\mathrm {r}}$ ) values, the capacitance ( $C$ ) values and the switching voltage ( $V_{\mathrm {c}}$ ) of this MFIS gate structure decreased with the increasing total dose. A TCAD model of Metal/HfAlO/SiO2/Si (MFIS) was proposed to explain the degradation mechanism of ferroelectric properties of the MFIS structure. We find that the new interface defects caused by radiation can reduce the electric field strength with the increasing total dose, which can significantly influence the irradiation properties of the HfAlO/SiO2/n-Si gate structure. These results provide the basis to applications for the HfO2-based devices in radiation working environment.

Electrical properties of Pb[Zr0.35Ti0.65]O3 on PEALD Al2O3 for NVM applications

PurposeDevelopment of (1T-type) ferroelectric random access memory (FeRAM) has most actively progressed since 1995 and motivated by the physical limits and technological drawbacks of the flash memory. 1T-type FeRAM implements ferroelectric layer at the field effect transistor (FET) gate. During the course of the investigation, it was very difficult to form a thermodynamically stable ferroelectric-semiconductor interface at the FET gate, leading to the introduction of one insulating buffer layer between the ferroelectric and the silicon substrate to overcome this problem. In this study, Al2O3 a high-k buffer layer deposited by plasma enhanced atomic layer deposition (PEALD) is sandwiched between the ferroelectric layer and silicon substrate.Design/methodology/approachFerroelectric/high-k gate stack were fabricated on the silicon substrate and pt electrode. Structural characteristics of the ferroelectric (PZT) and high-k (Al2O3) thin film deposited by RF sputtering and PEALD, respectively, were optimized and investigated for different process parameters. Metal/PZT/Metal, Metal/PZT/Silicon, Metal/PZT/Al2O3/Silicon structures were fabricated and electrically characterized to obtain the memory window, leakage current, hysteresis, PUND, endurance and breakdown characteristics.FindingsXRD pattern shows the ferroelectric perovskite thin Pb[Zr0.35Ti0.65]O3 film with (101) tetragonal orientation deposited by sputtering and PEALD Al2O3 with (312) orientation showing amorphous nature. Multiple angle analysis shows that the refractive index of PZT varies from 2.248 to 2.569, and PEALD Al2O3 varies from 1.6560 to 1.6957 with post-deposition annealing temperature. Increase in memory window from 2.3 to 8.4 V for the Metal-Ferroelectric-Silicon (MFS) and Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been observed at the annealing temperature of 500°C. MFIS structure with 10 nm buffer layer shows excellent endurance of 3 × 109 read-write cycles and the breakdown voltage of 33 V.Originality/valueThis paper shows the feature, principle and improvement in the electrical properties of the fabricated gate stack for 1T-type nonvolatile FeFET. The insulating buffer layer sandwiched between ferroelectric and silicon substrate acts as a barrier to ferroelectric–silicon interdiffusion improves the leakage current, memory window, endurance and breakdown voltage. This is perhaps the first time that the combination of sputtered PZT on the PEALD Al2O3 layer is being reported.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.

Integration and Electrical Properties of Ferroelectric Hf0.5Zr0.5O2 Thin Film on Bulk β-Ga2O3(-201) Substrate for Memory Applications

Metal–ferroelectric–insulator–semiconductor (MFIS) structures with wide bandgap semiconductors are promising for high temperature, radiation-hard, and high-density memory applications, but the insufficient scalability of perovskite-based ferroelectric thin films and the high cost of conventional wide bandgap semiconductors are the most serious barriers for their practical applications. Here, we integrate highly scalable ferroelectric Hf0.5Zr0.5O2 (HZO) thin films on potentially low-cost bulk $\beta$ -Ga2O3substrates using an Al2O3 buffer layer to form MFIS structures and investigate the microstructural and electrical properties of the HZO thin films and TaN/HZO/Al2O3/ $\beta$ -Ga2O3(−201) MFIS structures. We find that the TaN/HZO/Al2O3/ $\beta$ -Ga2O3(−201) MFIS structure annealed at 550 °C exhibits a memory effect, which is attributed to the ferroelectricity of the HZO thin film. This letter represents the critical first step in the implementation of $\beta$ -Ga2O3in HfO2-based ferroelectric memories.

Low-voltage-driven Pt/BiFeO3/DyScO3/p-Si-based metal–ferroelectric–insulator–semiconductor device for non-volatile memory

In recent years, ferroelectric random access memory has drawn considerable attention as promising replacement to both dynamic random access memory and flash memory. Specifically in metal–ferroelectric–insulator–semiconductor (MFIS)-based structures, bi-stable polarization of ferroelectric gate even in absence of power holds the resistance state of semiconductor-drain channel between two logic states and offers additional features of non-destructive readout and non-volatile storage capability. However, insulating layer in such structure leads to high depolarizing field across FE layer and in turn high-voltage operation. In the present work, comprehensive performance of low-voltage-driven MFIS device, i.e., Pt (40 nm)/BiFeO3 (265 nm)/DyScO3 (6 nm)/Si is evaluated for gate voltage stress (± 2 to ± 9 V) at different thermal agitation (200–400 K). Fat capacitance–voltage (C–V) hysteresis centered at zero bias with large memory window (ΔV FB) of 1.9 V at low operating voltage of ± 5 V, and stable data retention with distinguishable ON/OFF state values specifies strong charge storage potential of MFIS device in extreme conditions of ± 100 K. X-ray diffraction revealed polycrystalline and rhombohedral R3c phase of BiFeO3 film and out-of-plane piezoresponse force microscopy analysis showed the ultrafast domain switching with sharp contrast. Complete 180° phase reversal in hysteresis loop and bufferfly-shaped piezo-actuation amplitude loop further confirmed the enhanced ferroelectric properties of BiFeO3 thin films. Nonlinear J–V curves of MFIS structure were investigated to understand the device reliability and charge transport mechanism. These encouraging results are crucial for designing more reliable integrated MFIS-based non-destructive readout non-volatile memory devices.

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure.

Modeling and simulation of ionizing radiation effect on ferroelectric field-effect transistor

A theoretical model is developed to investigate the ionizing radiation effect on electrical characteristics of a metal–ferroelectric–insulator–semiconductor structure ferroelectric gate field-effect transistor (MFIS FeFET). Modeling results show that gate capacitance versus gate voltage curves and transfer characteristic curves shift significantly and the memory window becomes worse with the total dose. Moreover, the drain current and ION/IOFF ratio exhibit a considerable decrease under high incident dose rates. Finally, it is found that radiation-induced degradations can be affected strongly by the insulator layer thickness, and that MFIS FeFETs with a thin insulator buffer layer show a high radiation tolerance.

Analytical drain current model for long-channel gate-all-around negative capacitance transistors with a metal–ferroelectric–insulator–semiconductor structure

A carrier-based analytical drain current model was proposed for long-channel gate-all-around negative capacitance transistors with a metal–ferroelectric–insulator–semiconductor structure, which was derived by solving Poisson’s equation and a one-dimensional Landau–Khalatnikov equation. The electrostatic potential, gain of surface potential, and drain current were examined extensively by changing different device parameters, including the ferroelectric film thickness, channel radius, insulator layer thickness, and permittivity of the insulator layer. The device design methodologies are discussed in detail in this paper. A nonhysteretic transfer characteristic with a steep subthreshold swing (<60 mV/decade) was achieved at room temperature by optimizing the device parameters. The developed model is valid for all operation regions without any auxiliary variables or functions.

Ionizing radiation effect on metal–ferroelectric–insulator–semiconductor memory capacitors

A theoretical model was developed to investigate the ionizing radiation effect on the electrical characteristics of metal–ferroelectric–insulator–semiconductor (MFIS) structure capacitors under exposure to radiation and under post-irradiation conditions. In this model, the radiation-induced degradation in the ferroelectric layer, oxide layer and silicon dioxide interface were considered, and the radiation effect of the silicon substrate was also taken into account to accommodate the dose rate effect. The modeling results showed that both the capacitance versus applied voltage (C–V) curves and the surface potential versus applied voltage (ΦS(Si)–V) curves shifted significantly and the memory window became worse with increasing total dose. Moreover, the derived results indicated that the symmetry of the polarization versus applied voltage (P–V) curves degraded with the increase in total dose, which may explain the phenomena of radiation-induced fatigue and imprint. These results can provide some insights into the estimation of the radiation-induced degradation of MFIS structure devices and may be integrated into electronic design automation (EDA) software for ionizing radiation effect simulation.

Lead Free Metal-Ferroelectric-Insulator-Semiconductor Devices for Non-Volatile Memory Appliactions

The polarization bistability of the ferroelectric material offers the possibility to develop dense, energy efficient, fast and non volatile ferroelctric random access memory (FeRAM) with long retention and high endurance, as a promising replacement to both DRAM and Flash for the continued scaling. With this motivation, metal-ferroelectric-insulator-semiconductor (MFIS) structures were fabricated on p-Si <100> semiconductor substrate, by first depositing a 6 nm thick amorphous DyScO3 high-k insulator layer using metal organic chemical vapor deposition (MOCVD), followed by a 265 nm thick polycrystalline BiFeO3 (BFO) ferroelectric layer employing radio frequency (RF) sputtering, and finally a 40 nm thick platinum metal layer by DC magnetron sputtering. Electrical properties of the developed MFIS (Pt/BiFeO3/DyScO3/SiOx/Si) stacks were characterized as a function of thermal agitation (200 K to 400 K) to evaluate their device performance. Fat hysteresis loop was observed in the frequency dependent (1 kHz-1 MHz) capacitance-voltage (C-V) measurement with a memory window (ΔVFB) of 0.8 V at an exceptionally very low sweep voltage of ± 2 V. The memory window increased to 2.2 V as the sweep voltage was raised to ± 4 V and beyond up to ± 8 V, indicating a highly stable device. Low leakage current (1.2 μA/cm2 at 4 V) and excellent data retention characteristics with distinguishable high and low capacitance values over the long time period of 106 sec, revealed strong charge storage potential of the fabricated device architecture. The non-linear hysteretic J-E curves of the MFIS structure were also investigated in detail as a function of temperature to understand the device reliability and the charge transport mechanisms. Piezoelectric force microscopy (PFM) and P-E hysteresis loop (domains reversal) studies were carried out to confirm the ferroelectric nature of the polycrystalline BFO thin films. The encouraging results achieved reveals that Pt/BiFeO3/DyScO3/SiOx/Si MFIS device architecture is a promising one for realization of FeRAM devices.

Modeling of metal-ferroelectric-insulator-semiconductor structure considering the effects of interface traps

An improved model, in which the interface traps effects are considered, is developed by combining with quantum mechanical model, dipole switching theory and silicon physics of metal-oxide-semiconductor structure to describe the electrical properties of metal-ferroelectric-insulator-semiconductor (MFIS) structure. Using the model, the effects of the interface traps on the surface potential ( ϕ Si ) of the semiconductor, the low frequency (LF) capacitance-voltage ( C-V ) characteristics and memory window of MFIS structure are simulated, and the results show that the ϕ Si - V and LF C-V curves are shifted toward the positive-voltage direction and the memory window become worse as the density of the interface trap states increases. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the improved model can be integrated into electronic design automation (EDA) software for circuit simulation.

Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiOxNy) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm2 under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiOxNy buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (CH) and low (CL) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiOxNy, respectively. Thus, Au/PZT/TiOxNy/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.

Ferroelectric characteristics of MFIS structure with P(VDF–TrFE)/BaTiO3 nanocomposite as ferroelectric layer

A metal–ferroelectric–insulator–semiconductor (MFIS) structure has been made using poly(vinylidene difluoride–trifluoroethylene)/barium titanate [P(VDF–TrFE)/BaTiO3] nanocomposite as ferroelectric layer, on silicon/silicon dioxide (Si/SiO2) substrate. Different concentrations of BaTiO3 were added to P(VDF–TrFE) polymer using bath sonication method, and the films were prepared using spin coating method. The structure was annealed to 120 °C for 2 h and then the top aluminium electrode was deposited by thermal evaporation method. Capacitance–voltage shows an increase in accumulation capacitance as the BaTiO3 nanoparticle concentrations increases. Dielectric constant was estimated from the capacitance voltage (C–V) characteristics and found to be changing as the concentration of BaTiO3 is varied. Polarization–electric field analyses show hysteresis behaviour of the nanocomposite. A comparison of MFIS and metal–ferroelectric–semiconductor structures was done with varying ferroelectric film thicknesses. All these results suggest that this polymer nanocomposite can be a promising material which can be used in non-volatile memory devices.