Analytical drain current model for long-channel gate-all-around negative capacitance transistors with a metal–ferroelectric–insulator–semiconductor structure

Abstract

A carrier-based analytical drain current model was proposed for long-channel gate-all-around negative capacitance transistors with a metal–ferroelectric–insulator–semiconductor structure, which was derived by solving Poisson’s equation and a one-dimensional Landau–Khalatnikov equation. The electrostatic potential, gain of surface potential, and drain current were examined extensively by changing different device parameters, including the ferroelectric film thickness, channel radius, insulator layer thickness, and permittivity of the insulator layer. The device design methodologies are discussed in detail in this paper. A nonhysteretic transfer characteristic with a steep subthreshold swing (<60 mV/decade) was achieved at room temperature by optimizing the device parameters. The developed model is valid for all operation regions without any auxiliary variables or functions.