Logic Memory Research Articles

Implementation of Memristor Towards Better Hardware/Software Security Design

The latest electronic devices are seeking much smaller CMOS devices but limitless scaling down of CMOS transistor leads to degradation in its performance. The classical security systems designed with CMOS devices are prone to physical and side-channel attacks. The missing element “Memristor” whose concept was proposed by Leon Chua is becoming the best choice for emerging hardware security design. Few characteristics of memristor which observed at the beginning seem to be problematic have turned into a blessing for security design and these characteristics are bi-directionality, process variation, non-volatility, and radiation hardness. Due to ultralow power consumption and high computational speed, memristors are drawing the attention of researchers as it also is useful in digital memory design, neuromorphic systems, logic circuits, and hardware security systems. In this manuscript, various memristor applications in hardware and software security systems will be focused on. It comprises a memristor-based physically unclonable function (PUF), which became novel security primitive. Memristor applications are also explained in a true random number generator by which the security of the digital transaction can be improved. The tamper detection circuits developed with memristors are capable to detect the tampering of the secret information in smart cards and therefore memristor-based tamper sensitive circuits are also briefed here to protect the secret data. Finally, the utilization of the memristor in the forensics, crypto architecture, and neuromorphic security systems are explained which will enhance the memristor applicability in the designing of advanced information protection digital circuits and systems.

The emergence of carbon-dots for optical molecular electronics: from sensors to logic gates, memory devices, and security

In this article, the molecular electronics potential of c-dots and their applications as molecular logic gates, keypad lock, memory devices, and complex circuits is elucidated.

Ga2O3 based multilevel solar-blind photomemory array with logic, arithmetic, and image storage functions.

Photomemories offer great opportunities for multifunctional integration of optical sensing, data storage, and processing into one single device. However, little attention has been paid to photomemories working in the solar-blind region so far, which may have unique advantages of insusceptibility to ambient light and higher capacity. Herein, we propose and demonstrate a Ga2O3 based solar-blind photomemory array with logic, arithmetic, and optoelectronic memory functions. The device shows n-type field effect-transistor performance with an on/off ratio as high as 106, a responsivity of 8 × 103 A W-1, and a detectivity of 1.42 × 1014 Jones, all of which are amongst the best values ever reported for Ga2O3 based photodetectors. Based on the trapping and de-trapping process of holes in Ga2O3, multilevel data storage can be realized from the device. Simultaneously, the optical and electrical mixed basic logic of reconfigurable "AND" and "OR" operations have been realized in a single cell through the co-regulation of solar-blind light and the grid voltage. In addition, the photomemory can perform counting and addition operations, and the photomemory array can be utilized to realize solar-blind image storage. The results suggest that Ga2O3 may have potential applications in high-performance information storage, computing, and communications.

A wafer-scale synthesis of monolayer MoS2 and their field-effect transistors toward practical applications.

Molybdenum disulfide (MoS2) has attracted considerable research interest as a promising candidate for downscaling integrated electronics due to the special two-dimensional structure and unique physicochemical properties. However, it is still challenging to achieve large-area MoS2 monolayers with desired material quality and electrical properties to fulfill the requirement for practical applications. Recently, a variety of investigations have focused on wafer-scale monolayer MoS2 synthesis with high-quality. The 2D MoS2 field-effect transistor (MoS2-FET) array with different configurations utilizes the high-quality MoS2 film as channels and exhibits favorable performance. In this review, we illustrated the latest research advances in wafer-scale monolayer MoS2 synthesis by different methods, including Au-assisted exfoliation, CVD, thin film sulfurization, MOCVD, ALD, VLS method, and the thermolysis of thiosalts. Then, an overview of MoS2-FET developments was provided based on large-area MoS2 film with different device configurations and performances. The different applications of MoS2-FET in logic circuits, basic memory devices, and integrated photodetectors were also summarized. Lastly, we considered the perspective and challenges based on wafer-scale monolayer MoS2 synthesis and MoS2-FET for developing practical applications in next-generation integrated electronics and flexible optoelectronics.

Realization of a Sub 10-nm Silicene Magnetic Tunnel Junction and Its Application for Magnetic Random Access Memory and Digital Logic

Silicene has attracted the research interest due to its excellent electronic and spin properties. Furthermore, CrO2 half metal due to its high Curie temperature and high spin polarization is well suited for electrodes. In this work, we have simulated the magnetic tunnel junction device consisting of CrO2 electrodes and Silicene as a scattering region. The device is in a sub 10-nm regime, hence supports high integration density. The bias dependent spin transport properties (I-V characteristics and transmission spectrum) of the modeled device were calculated by Atomistic Tool Kit software, which uses density functional theory and non-equilibrium Greens function formalism. The device shows large tunnel magnetoresistance of 640%, depicting the potential application of the proposed device. The spin-dependent transmission spectrum, band structure, semi-conductor theory has been discussed to explain the origin of the spin-dependent transport characteristics. Moreover, an efficient method for MRAM (magnetic random access memory) read/write operation has been discussed. Furthermore, a NAND gate from a single modeled MTJ device has been realized, a half adder has also been realized from the modeled device to explore the potential of the modeled device for the implementation of complex digital functions.

CMOS back-end compatible memristors for in situ digital and neuromorphic computing applications.

In-memory logic calculations and brain-inspired artificial synaptic neuromorphic computing are expected to solve the limitations of the traditional von Neumann computing architecture. The data processing efficiency of the traditional von Neumann architecture is inherently limited by its physically separated processing and storage units, and thus data transmission besides calculation leads to a limited calculation speed and additional high-power consumption. In addition, traditional digital logic calculations and analog calculations have greater limitations in conversion. Herein, we report a flexible two-terminal memristor based on SiCO:H, which is a porous low-k back-end complementary metal-oxide-semiconductor (CMOS)-compatible material. Due to its low operating voltage (200 mV) and fast response speed (100 ns), it could perform digital memory calculation and neuromorphic calculation simultaneously. The memristor could realize a transition from short-term to long-term plasticity in the process of enhancement and inhibition during neuromorphic calculation, with high biological reality. In digital logic calculations, IMP-based and MAGIC-based logic calculations were verified. In neuromorphic computing, an Ag ion-based conductive filament was introduced. The relationship between the temporal dynamics of the conductance evolution and the diffusive dynamics of the Ag active metal could be modulated by the external programming electric field strength. The synapses and neuron dynamics in biology were faithfully simulated, realizing a transition from short-term to long-term plasticity in the process of enhancement and inhibition, which has high compatibility and scalability, proposing a novel solution for the next generation of computer architectures.

Gripe espanhola: fluxos encadeados de memória e lapidação das lembranças

Por meio da autoetnografia, na qual a experiência do pesquisador se inter-relaciona com o cenário empírico que analisa, o artigo desenvolve como se articulam, em atos comunicacionais, os flxos encadeados de memória, haja vista um evento traumático contemporâneo. A pandemia da Covid-19 faz emergir lembranças de um passado que sobreviveu pelas narrativas de outro, a gripe espanhola de 1918, nas memórias de infância de quem hoje faz o gesto de contar essa história. Apresentam-se, ainda, aspectos da cobertura jornalística realizada na época pelos principais periódicos do Rio de Janeiro que também produzem narrativas governadas pela lógica dos flxos encadeados de memória.

A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure

A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the conventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching probability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.

Excellent Reliability and High-Speed Antiferroelectric HfZrO2 Tunnel Junction by a High-Pressure Annealing Process and Built-In Bias Engineering

Hafnia-based ferroelectric tunnel junctions (FTJs) have great potential for use in logic in nonvolatile memory because of their complementary metal-oxide-semiconductor process compatibility, low power consumption, high scalability, and nondestructive readout. However, typically, ferroelectrics have a depolarization field, resulting in poor endurance owing to the early dielectric breakdown. Herein, an outstandingly reliable and high-speed antiferroelectric HfZrO tunnel junction (AFTJ) is probed to understand whether it is a promising candidate for next-generation nonvolatile memory applications. High-reliability AFTJ can be explained by less charge injection due to the low depolarized field. The formation of two stable nonvolatile states, even with antiferroelectric materials, is possible if asymmetric work function electrodes and fixed oxide charges are employed, generating a built-in bias and shifting the polarization-voltage curve. In addition, via high-pressure annealing, a critical voltage that determines the transition from the t-phase to the o-phase is effectively reduced (22%). The AFTJ shows a higher endurance property (>109 cycles) and faster switching speed (<30 ns) than FTJ. Hence, it is proposed that with the help of internal bias modulation and high-pressure annealing, AFTJs can be employed in next-generation memory devices.

Progress in designing novel single-phase room temperature multiferroics

Magnetoelectric multiferroics, because of their coupled electric and magnetic ordering in a single phase, are eminent for applications in logic and nonvolatile memory devices. Recent advances in computational modeling, synthesis, and characterization techniques are spurring significant advances in the study of these materials. During last several years, our group at University of Puerto Rico has been involved in synthesizing novel single-phase room temperature multiferroic materials that included not only solid solutions of lead zirconate titanate with lead iron tungstate, lead iron niobate, and lead iron tantalate, but also recently discovered palladium substituted room temperature multiferroics, namely PbPd0.3Ti0.7O3 and Pb(Zr0.2Ti0.8)Pd0.3O3. In this review, we have reported thin films of the above materials that were synthesized using pulsed laser deposition technique on various substrates at Speclab, University of Puerto Rico. We describe in detail thin film fabrication, structural diffraction analyses (XRD, TEM), dielectric, ferroelectric, piezo-response force microscopy, and magnetization results on recently grown Pd-substituted lead titanate and lead zirconate titanate thin films in an elaborate manner. The films were phase pure and stabilized in c-axis oriented tetragonal phase (P4mm) with surface roughness RQ of 2–4 nm. Temperature-dependent dielectric studies on metal-dielectric-metal heterostructure capacitors indicate that ferroelectric to paraelectric phase transition is above 500 K. A proof of ferroelectricity was confirmed from strong domain switching responses using piezo-response force microscopy. These films showed ferromagnetic ordering below 395 K. The origin of magnetic ordering in these materials was attributed to the existence of Pd2+ and Pd4+ mixed oxidation states of palladium dispersed in the polar matrices. We conclude with the above findings that these multiferroics may have potential applications.in nonvolatile memory and other multifunctional devices.

Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices

Edge computing has been shown to be a promising solution that could relax the burden imposed onto the network infrastructure by the increasing amount of data produced by smart devices. However, reconfigurable ultra-low power computing architectures are needed. RRAM devices together with the material implication logic (IMPLY) are a promising solution for the development of low-power reconfigurable logic-in-memory (LiM) hardware. Nevertheless, traditional approaches suffer from several issues introduced by the circuit topology and device non-idealities. Recently, SIMPLY, a smart LiM architecture based on the IMPLY, has been proposed and shown to solve the common issues of traditional architectures. Here, we use a physics-based RRAM compact model calibrated on three RRAM technologies to further analyze the performance of SIMPLY in typical operating conditions, when the repeated execution of logic operation on the same group of devices is considered. The results show that, compared to the conventional IMPLY architecture, SIMPLY spares more than 40% of the high voltage pulses on average even when complex operations are considered (e.g., the 1-bit half adder). We also show how SIMPLY can implement the set of operations required for the implementation of Binarized Neural Networks (BNN) and benchmark its performance against other memristor-based BNN in-memory accelerator from the literature. The results suggest that our approach is more than two orders of magnitude efficient compared to the state of the art reconfigurable in-memory computing approach and could potentially reach the performance of specialized BNN analog hardware accelerators with appropriate device-circuit co-design strategies.

Picene and PTCDI based solution processable ambipolar OFETs

Facile and efficient solution-processed bottom gate top contact organic field-effect transistor was fabricated by employing the active layer of picene (donor, D) and N,N′-di(dodecyl)-perylene-3,4,9,10-tetracarboxylic diimide (acceptor, A). Balanced hole (0.12 cm2/Vs) and electron (0.10 cm2/Vs) mobility with Ion/off of 104 ratio were obtained for 1:1 ratio of D/A blend. On increasing the ratio of either D or A, the charge carrier mobility and Ion/off ratio improved than that of the pristine molecules. Maximum hole (µmax,h) and electron mobilities (µmax,e) were achieved up to 0.44 cm2/Vs for 3:1 and 0.25 cm2/Vs for 1:3, (D/A) respectively. This improvement is due to the donor phase function as the trap center for minority holes and decreased trap density of the dielectric layer, and vice versa. High ionization potential (− 5.71 eV) of 3:1 and lower electron affinity of (− 3.09 eV) of 1:3 supports the fine tuning of frontier molecular orbitals in the blend. The additional peak formed for the blends at high negative potential of − 1.3 V in cyclic voltammetry supports the molecular level electronic interactions of D and A. Thermal studies supported the high thermal stability of D/A blends and SEM analysis of thin films indicated their efficient molecular packing. Quasi-π–π stacking owing to the large π conjugated plane and the crystallinity of the films are well proved by GIXRD. DFT calculations also supported the electronic distribution of the molecules. The electron density of states (DOS) of pristine D and A molecules specifies the non-negligible interaction coupling among the molecules. This D/A pair has unlimited prospective for plentiful electronic applications in non-volatile memory devices, inverters and logic circuits.

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies

In this era of nanoscale technologies, the inherent characteristics of some nonvolatile devices, such as resistive random access memory (ReRAM), phase-change material (PCM), and spintronics, can emulate stochastic functionalities. Traditionally, these devices have been engineered to suppress the stochastic switching behavior as it poses reliability concerns for memory storage and logic applications. However, leveraging stochasticity in such devices led to a renewed interest in hardware-software codesign of stochastic algorithms since the CMOS-based implementations of stochastic algorithms involve cumbersome circuitry to generate “stochastic bits.” In this article, we consider two classes of problems: deep neural networks (DNNs) and combinatorial optimization. The rapidly growing demands of artificial intelligence (AI) have sparked an interest in energy-efficient implementations of large DNNs, with binary representations of synaptic weights and neuronal activities. Stochasticity plays an important role in leveraging the benefits of these binary representations, leading to model compression and optimization during training. In combinatorial optimization, such as graph coloring or traveling salesman problems, stochastic algorithms, such as the Ising computing model, have been shown to be effective. These problems require exhaustive computational procedures, and the Ising model uses a natural annealing agent to achieve near-optimal solutions in a reasonable timescale, without getting stuck in “local minima.” In this article, we present a broad review of stochastic computing utilizing the stochastic switching characteristics of devices based on nanoscale nonvolatile technologies. We show how to codesign of the devices and algorithms that can enable optimal solutions for both combinatorial problems and binary neural networks for local learning and inference. Directly mapping the nonvolatile device characteristics to the stochastic algorithms without the need for storing the bits in a separate memory leads to efficient use of hardware.

(Invited) Advanced ALD Applications

CMOS device feature size down-scaling is still continuous. Nowadays it reaches 5nm and beyond. The technology development in semiconductor industry encounters many new challenges. As consequences, new materials and new techniques are required to meet the challenges.At 45nm technology node, Atomic Layer Deposition (ALD) is introduced for gate stack process. Since then ALD is being used more and more in advanced technology nodes because of its intrinsic process features, e.g. accurate thickness control and excellent step coverage etc. Especially for the reduced feature sizes, ALD exhibits as a powerful technique, not only in gate stack, but also in advanced patterning process (SADP and SAQP) and advanced metallization barrier materials etc.Hf-based hik material deposited by ALD is widely used in logic gate stack and memory capacitor. Recently Hf-based materials are continuously getting more attentions due to its intrinsic features. It is reported that Hf-based materials can exhibit different resistor stage. Therefore it can be used as memristor in ReRAM. People also report Hf-based materials can be crystalized into orthorhombic phase and thus exhibit ferroelectric characteristics[1,3]. Based on this feature, it can be used in NCFET and FeRAM. In this paper, we can going to review the applications of Hf-based materials deposited by ALD in new memory fields.Although device down-scaling is still going on, the challenges are tremendous. As an alternative, 3D-IC packaging, stacks different chip together and increases the packaging density and chip performance. Therefore, recently 3D-IC packaging is getting more and more attractive. However, there are many constrains in 3D-IC packaging, e.g. low thermal budget, high aspect ratio structure, excellent film quality etc.. ALD is gradually accepted in 3D-IC packaging due to its intrinsic features. In this paper, we are going to discuss some ALD applications in advanced 3D-IC packaging.REFERENCES[1] J. Müller et al, NanoLetters, vol. 12, no. 8, pp. 4318-4323, 2012.[2] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.[3] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.

Comparative Study of Titanium Nitride ALD using High Purity Hydrazine vs Ammonia

Emerging devices (Logic and Advanced Memory) require high quality thin (5-20 Å) electrode and barrier films. Difficult thermal budget constraints are now being placed on well-known materials such as TiN and TaN. Deposition temperature limitations have reached 350°C and below while very low resistivity (<100 micro-ohm/cm) must be achieved. Novel Ti precursors are being explored.1 Our approach has focused on hydrazine (N2H4) as an alternative nitrogen source to NH3.Hydrazine is generally difficult to handle from a safety perspective due to its flammability and toxicity. We have developed a novel method to store and generate hydrazine in situ as a high purity gas which is then delivered to ALD process chambers.2 In this study, we examine the effect that hydrazine has on low deposition temperature TiN ALD processes. We experimentally evaluate TiN ALD growth and film characteristics using TiCl4/ N2H4 in comparison to that using TiCl4/NH3.Titanium Nitride films were deposited using the hot wall type tubular furnace and a sequential gas supply system. Deposition temperature was set to predetermined value in the range from 250°C to 400°C. In the case of TiCl4/NH3, GPC was 0.10-0.27 Å/cycle at 250-400°C, where a decrease is noted as the deposition temperature is reduced. With the use of hydrazine, an increase in GPC is observed at each deposition temperature vs NH3. Moreover, the temperature dependence of GPC moved in the opposite direction of TiCl4/NH3. Specifically, GPC of TiCl4/N2H4 ALD was 19% higher at 400°C while an increase of 310% was seen at 250°C versus NH3. In the case of TiCl4/N2H4, the ALD window appears in the range of 250-400°C, where TiCl4 adsorption saturation curves are observed at 250°C and 400°C. Refractive index (R.I.) of TiCl4/N2H4 ALD was about 1.68-1.73 at 250-400°C. These values were approximately equal to R.I. of typical sputtered TiN which was about 1.66. In contrast, R.I. of TiCl4/NH3 ALD was larger than 2.00 in the 250- 300°C range. Because of R.I. of typical titanium oxide is about 2.4-2.5, it is assumed that the TiCl4/NH3 ALD film is contaminated by oxygen. In the ammonia case, background contaminants in the reactor appear to compete with low reactivity NH3 for reaction sites on the ALD surface. In the TiCl4/N2H4 case, higher temperature is not required to form high quality TiN films compared to TiCl4/NH3 ALD.From the above results, the use of high purity hydrazine is beneficial to maintaining high throughput and good film quality under the new constraints for emerging devices. Film composition by XPS and Resistivity measurements consistent with this conclusion will also be presented.

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory dot-product for neural networks. The proposed architecture allows the NVM operations in both 2T2R and conventional 1T1R configurations. The proposed LiM full adder (LiM-FA) improves the delay, the static power, and the dynamic power by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> , respectively, compared with state-of-the-art LiM-FAs. Furthermore, based on different optimization techniques and robustness analysis, a lower precharge voltage is set for each mode. This reduces the TCAM search energy and 1T1R ReRAM access energy by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.14\times $ </tex-math></inline-formula> , respectively, compared with the case without optimizations.

Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.

Ultrathin flexible InGaZnO transistor for implementing multiple functions with a very small circuit footprint

There is a continuous demand to reduce the size of the devices that form a unit circuit, such as logic gates and memory, to reduce their footprint and increase device integration. In order to achieve a highly efficient circuit architecture, optimizations need to be made in terms of device processing. However, the time involved in the current reduction of device sizes according to Moore’s Law has slowed down. Here, we propose a flexible transistor with ultra-thin IGZO (InGaZnO, indium-gallium-zinc-oxide) as the channel material, which not only scales down the footprints of multi-transistor logic gates but also combines the functions of the logic gates, memory, and sensors into a single cell. The transistor proposed here has an ultrathin semiconductor layer and can implement the typical functions of logic gates that conventionally have 2–6 transistors. Furthermore, it demonstrates the memory effect with a programming time as low as 5 ns. This design can also display various artificial synaptic behaviors. This new device design and structure can be adopted for the development of next-generation flexible electronics that require higher integration.

Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration

High parallelism degree is fundamental for high speed massive data processing systems. Modern FPGA devices can provide such parallelism plus flexibility. However, these devices are still limited by their logic block size, memory size, memory bandwidth and configuration time. Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. This approach can increase the effective area for system implementation, allowing increase of parallelism in each task that composes the application. However, the necessary reconfiguration time between contexts can cause performance decrease. A possible solution for this is an intensive parallelism exploration of massive data application to compensate for this overhead and improve global performance. This is true for modern FPGA with relatively high reconfiguration speed. In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the application task scheduling. A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. Experiments demonstrate the efficiency of this approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration. A design flow is shown based on library components that implements typical tasks used in the domain of applications.

Electric field control of three-dimensional vortex states in core-shell ferroelectric nanoparticles

The fundamental question whether the structure of curled topological states, such as ferroelectric vortices, can be controlled by the application of an irrotational electric field is open. In this work, we studied the influence of irrotational external electric fields on the formation, evolution, and relaxation of ferroelectric vortices in spherical nanoparticles. In the framework of the Landau-Ginzburg-Devonshire approach coupled with electrostatic equations, we performed finite element modeling of the polarization behavior in a ferroelectric barium titanate core covered with a “tunable” paraelectric strontium titanate shell placed in a polymer or liquid medium.A stable two-dimensional vortex is formed in the core after a zero-field relaxation of an initial random or poly-domain distribution of the polarization, where the vortex axis is directed along one of the core crystallographic axes. Subsequently, sinusoidal pulses of a homogeneous electric field with variable period, strength, and direction are applied. The field-induced changes of the vortex structure consist in the appearance of an axial kernel in the form of a prolate nanodomain, the growth of the kernel, an increasing orientation of the polarization along the field, and the onset of a single-domain state. We introduced the term “kernel” to name the prolate nanodomain developed near the vortex axis and polarized perpendicular to the vortex plane. In ferromagnetism, this region is generally known as the vortex core.Unexpectedly, the in-field evolution of the polarization includes the formation of Bloch point structures, located at two diametrically opposite positions near the core surface. After removal of the electric field, the vortex recovers spontaneously; but its structure, axis orientation, and vorticity can be different from the initial state. As a rule, the final state is a stable three-dimensional polarization vortex with an axial dipolar kernel, which has a lower energy compared to the initial purely azimuthal vortex. The nature of this counterintuitive result is a significant gain of the negative Landau energy in the axial region of the vortex due to the formation of a kernel, which is only partially compensated by an increase in positive energy of the depolarization field, polarization gradient, and elastic stress for a vortex with a prolate single-domain kernel.The analysis of the torque and electrostatic forces acting on the core-shell nanoparticle in an irrotational electric field showed that the torque acting on the vortex with a kernel tends to rotate the nanoparticle in such way that the vortex axis becomes parallel to the field direction. The vortex (with or without a kernel) is electrostatically neutral, and therefore the force acting on the nanoparticle is absent for a homogeneous electric field, and nonzero for the field with a strong spatial gradient.The vortex states with a kernel possess a manifold degeneracy, appearing from three equiprobable directions of vortex axis, clockwise and counterclockwise directions of polarization rotation along the vortex axis, and two polarization directions in the kernel. This multitude of the vortex states in a single core is promising for applications of core-shell nanoparticles and their ensembles as multi-bit memory and related logic units. The rotation of a vortex kernel over a sphere, possible for the core-shell nanoparticles in a soft matter medium with controllable viscosity, may be used to imitate qubit features.