Efficient Memory Design Research Articles

Toward Memory-Efficient Analog Design Using Precomputed Lookup Tables

Analog design productivity remains a challenge in the digitally driven semiconductor chip design field. Knowledge-based and simulation-based analog automation approaches have not achieved widespread acceptance in the analog design community. Systematic analog design using precomputed lookup tables (LUTs) is a promising approach that can address the design productivity challenge. Although modern computing systems have powerful memory capabilities, which make the LUT approach viable, reducing the memory footprint of the LUTs remains a challenge. A memory-efficient design technique using LUTs is proposed by using an incomplete grid in the MOSFET degrees-of-freedom (DoFs) space. An efficient indexing technique for the incomplete grid is also proposed, using a precomputed offset array in various scenarios, such as two-sided constraints and three-dimensional LUTs. The results show that the proposed technique can achieve up to a 67% reduction in memory footprint, in addition to improving LUT generation time and query performance.

Area-Delay-Power Efficient VLSI Architecture 2D FIR Filter using Modified Multipliers and Adders

In this paper, a low power, area, and delay 2D Finite Impulse Response (FIR) filter architecture is derived from an analysis of a memory-efficient design. The completely direct-form 2D FIR filter is where the idea of parallel processing is first presented. As a result, the FIR filter may make better use of its memory by reusing its contents. With a block size of L and a filter length of N, a non-separable 2D FIR filter structure is developed and implemented. The FIR filter's arithmetic module makes use of high-speed, low-power multipliers and Carry Look Ahead (CLA) adders, with the output calculated by a pipelined adder unit. Verilog HDL code is used to represent the proposed architecture, and the CADENCE environment's NC Simulator and RTL Compiler synthesis tool are used to verify the design. Existing memory-efficient 2D FIR filter hardware architectures are compared to the produced area, power, and delay reports. Using Modified CLA (MCLA) adders and pipelining, we were able to cut down on power consumption by 44% and delay by 20%. Index Terms: Memory reuse, 2D-FIR filter, Low Power Multiplier, Parallel Prefix Adder, Carry Look Ahead adder, and pipelining.

Ultra-High Definition AV1 FME Interpolation Architectures Exploring Approximate Computing

Modern video encoders like the AOMedia Video 1 (AV1) implement several complex tools to allow the required high level of compression efficiency. The Fractional Motion Estimation (FME) is one of these complex tools, and AV1 FME defines 42 different interpolation filters. To handle such complexity, hardware acceleration using approximate computing has become an interesting alternative to be explored. This paper presents three optimized approximate architectures for the AV1 FME interpolation filters. The architectures reach real time interpolation for UHD 4K videos at 30 frames per second in a low cost, low power, and memory-efficient design. The architectures were synthesized for a 40nm TSMC standard-cells technology reaching power gains up to 83%, when compared to a precise architecture, and up to 20% when compared to a previously published approximated solution. The area gains were also expressive: up to 83% and 40%, respectively. The architectures also allow a memory bandwidth reduction of up to 59.5%, in comparison with the state-of-the-art solutions. The approximations implied small coding efficiency degradation of 0.54% and 1.25% in BD-BR. The presented architectures have the best results found in the literature when considering the trade-off among hardware cost, power dissipation, processing rate, memory bandwidth, and coding efficiency.

Physical-Layer Security for Frequency Diverse Array-Based Directional Modulation in Fluctuating Two-Ray Fading Channels

The frequency diverse array (FDA)-based directional modulation (DM) technology plays an important role in the physical-layer security (PLS) transmission of 5G and beyond communications. In order to meet the tremendous increase in mobile data traffic, a new memory-efficient design for the FDA-DM-based PLS transmission is urgently demanded. In this article, an analytical symmetrical multi-carrier FDA model is proposed in three dimensions, namely, range, azimuth angle, and elevation angle, differing from the conventional analytical approach with only range and azimuth angle considered. Then, a single-point (SP) artificial noise (AN) aided FDA-DM scheme is proposed, which reduces the memory consumption significantly compared with the conventional zero-forcing (ZF) and singular value decomposition (SVD) approaches. Moreover, the PLS performance of the proposed FDA-DM scheme is analyzed in fluctuating two-ray (FTR) fading channels for the first time, including the average secrecy capacity (ASC) and the secrecy outage probability (SOP). More importantly, the closed-form expressions for the lower bound on ASC and the upper bound on SOP are derived, respectively. The effectiveness of the analytical expressions is verified by numerical simulations. This work opens a way to lower the memory requirements for DM-based PLS transmission of 5G and beyond communications.

Design and Implementation of 16bit SRAM Using Quantum Dot Cellular Automata

The era of CMOS technology at the nanoscale will be going to replace with an unimaginable future by the opportunity of Quantum-dot cellular automata (QCA). The largest possible scope for constructing an elegant and efficient memory design is there with QCA technology. The suggested methodology and execution of a brand-new reminiscence cell shape primarily depends on QCA with a minimum delay, area, and complications is provided to develop a static random-access memory. This paper affords the circuit diagram and its execution of a 16-bit Static RAM with a new shape in QCA. Because of having powerful pipelining structure with in the QCA, this SRAM is very fast in executing operations. With a new shape of 4-bit width design for the 16-bit SRAM has applied in QCA. The ability of resulting read/write operations often with minimal delay is possible with this kind of SRAM design. Having a smaller number of majority gates and cells, the design of 16-bit decoders and multiplexers are represented. For getting rid from the adjoining hassle of intersecting labels, the new signal distribution network has been used to implement the SRAM with 2-to-4 decoders and 4-to-1 mux’s. The Quantum do CA-primarily depend on Static RAM cell turned into comparison with the Static RAM cell depended totally on CMOS. Consequences observed that the suggested Static RAM is more systematic in phrases of area, complexity, clock frequency, latency, throughput, and power in take.

Performance Assessment of Different VLSI Architectures for Data Comparators for Cost Effective Sorting Networks

Noise removal is one of the major requirements in image, speech and signal processing applications. Impulse noise removal in image processing uses median filters. For edge preservation in image processing this acts as one of the best alternative non-linear technique to linear filtering. Real time hardware implementation of median filters has major concern of sorting networks. Efficient VLSI implementation of sorting network in terms of hardware complexity is of greater importance. This work provides a comparison of existing six data comparators and also proposes three modified data comparators in terms of their hardware complexity, area, power and speed. All the comparators were designed using verilog HDL and were targeted for xa6slx4-3-csg225using Xilinx ISE 9.2i FPGA design suite. From the results Modified Twos Complement Based Data Comparator is the minimum area required architecture with maximum combinational path delay and also with minimum number of LUTs used. The drawback of this architecture is the maximum memory requirement. The Modified Multiplexer Based Data Comparator and Modified Decoder Based Data Comparator architectures are suitable for memory efficient design.

IP Network Stack in Ada 2012 and the Ravenscar Profile

This article presents Ada Embedded Network, a small network stack intended to be used by small embedded Ada applications running on ARM. It implements the standard ARP, IPv4, UDP, DNS and DHCP protocols on top of an Ethernet driver. Its memory efficient design allows it to run on the STM32F746 board. The article presents the components from the Ada implementation point of view. It highlights the Ada features that have been used and shows some benefits of the Ravenscar profile that have helped the project.

GPU-SME-kNN: Scalable and memory efficient kNN and lazy learning using GPUs

The k nearest neighbor (kNN) rule is one of the most used techniques in data mining and pattern recognition due to its simplicity and low identification error. However, the computational effort it requires is directly related to the dataset sizes, hence delivering a poor performance on large datasets. The use of graphics processing units (GPU) has improved the run-time performance of the kNN rule but the computational requirements of current approaches limit this performance as the dataset size increases.In this paper, we propose a new scalable and memory efficient design for a GPU-based kNN rule, called GPU-SME-kNN, that breaks the dependency between dataset size and memory footprint while delivering high performance. An experimental study of GPU-SME-kNN is presented showing a high performance, even in cases that other methods cannot address, while the computational requirements are suitable for most commercial GPU devices. Our design has also been applied to kNN-based lazy learning algorithms reducing run-times in a significant way.

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or subtractors, one small ROM module, a barrel shifter, and ((N-1)/2)+1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.