Design and Implementation of 16bit SRAM Using Quantum Dot Cellular Automata

Abstract

The era of CMOS technology at the nanoscale will be going to replace with an unimaginable future by the opportunity of Quantum-dot cellular automata (QCA). The largest possible scope for constructing an elegant and efficient memory design is there with QCA technology. The suggested methodology and execution of a brand-new reminiscence cell shape primarily depends on QCA with a minimum delay, area, and complications is provided to develop a static random-access memory. This paper affords the circuit diagram and its execution of a 16-bit Static RAM with a new shape in QCA. Because of having powerful pipelining structure with in the QCA, this SRAM is very fast in executing operations. With a new shape of 4-bit width design for the 16-bit SRAM has applied in QCA. The ability of resulting read/write operations often with minimal delay is possible with this kind of SRAM design. Having a smaller number of majority gates and cells, the design of 16-bit decoders and multiplexers are represented. For getting rid from the adjoining hassle of intersecting labels, the new signal distribution network has been used to implement the SRAM with 2-to-4 decoders and 4-to-1 mux’s. The Quantum do CA-primarily depend on Static RAM cell turned into comparison with the Static RAM cell depended totally on CMOS. Consequences observed that the suggested Static RAM is more systematic in phrases of area, complexity, clock frequency, latency, throughput, and power in take.