Performance Assessment of Different VLSI Architectures for Data Comparators for Cost Effective Sorting Networks

Abstract

Noise removal is one of the major requirements in image, speech and signal processing applications. Impulse noise removal in image processing uses median filters. For edge preservation in image processing this acts as one of the best alternative non-linear technique to linear filtering. Real time hardware implementation of median filters has major concern of sorting networks. Efficient VLSI implementation of sorting network in terms of hardware complexity is of greater importance. This work provides a comparison of existing six data comparators and also proposes three modified data comparators in terms of their hardware complexity, area, power and speed. All the comparators were designed using verilog HDL and were targeted for xa6slx4-3-csg225using Xilinx ISE 9.2i FPGA design suite. From the results Modified Twos Complement Based Data Comparator is the minimum area required architecture with maximum combinational path delay and also with minimum number of LUTs used. The drawback of this architecture is the maximum memory requirement. The Modified Multiplexer Based Data Comparator and Modified Decoder Based Data Comparator architectures are suitable for memory efficient design.