Memory Cell Circuit Research Articles

A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications

Computing-in-memory (CIM) suffers from remarkable area and performance costs from large memory cell and inefficient peripheral circuits for MLP acceleration. In this work, a 2D2R ReRAM CIM accelerator is proposed with circuit improvements for MLP in visual classification applications. The 2D2R ReRAM cell is organized as crossbar array for dense weight storage. The multi-level input circuit is proposed for high precision input with compensation for the nonlinearity of 2D2R cell. The successive-approximation output circuit is employed with all-0 detecting for fast and energy-efficient conversions. Besides, the weight-aware configurable computing is proposed to dynamically configure the input count for partial sum for improved performance. Compared with the traditional 2T2R cell, the area of 2D2R cell can be reduced by >85%. The accuracy of MNIST test set is 97.76% for the accuracy of 3b input, output and weight, and the energy efficiency can reach 174.5TOP/W under the working frequency of 200 MHz, realizing ∼2.6× improvement over previous work.

MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

Magnetic Nonvolatile SRAM Based on Voltage-Gated Spin-Orbit-Torque Magnetic Tunnel Junctions

This article proposes two different magnetic nonvolatile-static random access memory (MNV-SRAM) cell circuits for low-power, high-speed, and high-reliable backup operation with a compact cell area. They employ perpendicular magnetic tunnel junctions (p-MTJs) as nonvolatile backup storage elements and explore the spin-orbit torque (SOT) with the assistance of the voltage-controlled magnetic anisotropy effect (VCMA), referred to voltage-gated SOT (VGSOT), to perform the backup operation. By using an antiferromagnetic (AFM) layer that provides both an exchange bias and the SOT, no external magnetic field is required, making it suitable for practical applications. In addition, owing to the aid of the VCMA effect, the critical SOT write current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> ) for 1-ns backup operation can be reduced significantly, thus resulting in high speed, low power consumption, and high reliability. Moreover, such resulted I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SOT</sub> allows to be driven by the cross-coupled inverters in the SRAM cell, instead of a dedicated write driver, thereby leading to low cell area overhead. By using a commercial CMOS 40-nm design kit and a physics-based VGSOT-MTJ model, we have demonstrated their functionalities and evaluated their performance. Compared with previous SOT-based MNV-SRAM cell circuits, the proposed MNV-SRAM cell circuits can achieve lower backup energy dissipation, smaller backup delay, lower backup error rate and less cell area overhead without the assistance of the external magnetic field.

4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta-sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process. In view of area efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by [2 + (g' <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m1</sub> - 1) x A] times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master-slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits-at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.

Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.

Memory cell operation based on small Josephson junctions arrays

In this paper we analyze a cryogenic memory cell circuit based on a small coupled array of Josephson junctions. All the basic memory operations (e.g., write, read, and reset) are implemented on the same circuit and different junctions in the array can in principle be utilized for these operations. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics (SFQ). As an example, we demonstrate memory operation driven by a SFQ pulse employing an inductively coupled array of three Josephson junctions. We have chosen realistic Josephson junction parameters based on state-of-the-art fabrication capabilities and have calculated access times and access energies for basic memory cell operations. We also implemented an optimization procedure based on the simulated annealing algorithm to calculate the optimized and typical values of access times and access energies.

Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset

Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset). The proposed design is referred to as TDICE and uses transistors to block the paths that connect a node to the next node in the feedback loop of the memory cell circuit. The use of these transistors hardens the cell to tolerate a single event with a multiple-node upset at a large value of critical charge. Extensive simulation results are provided to assess TDICE with respect to traditional circuit figures of merit such as area, power consumption, and delay as well as PVT variations. The simulation results show that, at the expense of an increased area for the additional transistors, TDICE shows a nearly complete tolerance to a single event with a multiple-node upset.

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μ m 2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.

A Novel SET/MOSFET Hybrid Static Memory Cell Design

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated. A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the “1” and “0” logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the “1” and “0” logic states for a long period of time.

A monolithically integrated Si interband tunneling diode (IBTD)/MOSFET memory for ultra low voltage operation below 0.5 V

A static random access memory (SRAM) cell circuit, constructed using Si interband tunneling diodes (IBTDs) and a metal-oxide-semiconductor field effect transistor (MOSFET), is presented. The Si-IBTD is a negative differential resistance (NDR) device with a tunneling dielectric between a degenerate p+-diffusion layer and an n+-poly-Si electrode. The Si-IBTD was monolithically integrated with the MOSFET on a silicon-on-insulator (SOI) wafer by a novel fabrication process and a compact SRAM cell circuit consisting of two Si-IBTDs and a MOSFET was fabricated. The Si-IBTD shows a full process compatibility with a conventional MOSFET process. Data-read/write operations of this SRAM cell circuit were successfully demonstrated at ultra-low voltage, below 0.5 V, even at room temperature. Simulation results showed that downscaling of the Si-IBTD size was effective for improving the circuit speed. A writing time of the memory cell with a Si-IBTD size of 0.1 μ m2was reduced to 0.8 ns in simulation. The Si-IBTD/MOSFET merged SRAM can be considered one of the most promising candidates for future low-power device applications.

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 /spl mu/m CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b/spl times/256w) is 4.8 ns at 3.3 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fabrication and Evaluation of Three-Dimensional Optically Coupled Common Memory

A three-dimensional optically coupled common memory (3D-OCC memory) test chip, on which GaAs LEDs are integrated using the microbonding technique, has been fabricated using a 2 µ m complementary metal-oxide-semiconductor (CMOS) technology. Static memory cell circuits with photodiodes were formed on the chip. Optical writing and electrical reading operations of the 3D-OCC memory test chip have been demonstrated.

An integrated system for assigning signal flow directions to CMOS transistors

Signal flow direction information has been used to improve the accuracy and performance of many CAD tools. Hence deriving this information correctly and efficiently is an important and useful task. In this paper, an integrated system for deriving signal flow direction information in CMOS circuits is presented. This system consists of two subsystems: structure-based and rule-based. In the structure-based subsystem, a new graph-theoretic algorithm is used. The direction assignment problem is modeled as a two-paths problem on an undirected graph, called the global source target graph (GST-graph). The GST-graph is decomposed into split components by a linear time algorithm and the direction information of most edges in each split component can be derived by another linear time algorithm. If all transistors in a circuit are structurally unidirectional then their directions will be determined in this subsystem. Those transistors, if any, whose directions cannot be determined by this subsystem will be dealt with in the rule-based subsystem. A new set of rules including logic implication and precharge node driven rules have been developed. By considering circuit semantics, some difficult circuits such as a pass transistor based XOR gate, a six-transistor memory cell, barrel shifters, and precharge logic circuits can be processed. Experimental results show the accuracy and efficiency of this integrated system.

Simulation of a NDRO memory cell with very small excess current Josephson junctions

Abstract The dynamic behaviour of a single flux quantum NDRO interferometer cell with two very small excess current Josephson junctions is simulated for a clamping impedance parallel to the interferometer inductance. A proper design of the clamping impedance yields the required NDRO and written operations at large damping parameters β > 1000 of the Josephson junctions. Since large damping parameters are required for logic circuits the proposed NDRO memory cell and logic circuits can now be implemented with the same fabrication process.