Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset

Abstract

Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-node upset. This paper presents a novel memory cell design as variant of the DICE cell (that is tolerant to only a single event with a single-node upset). The proposed design is referred to as TDICE and uses transistors to block the paths that connect a node to the next node in the feedback loop of the memory cell circuit. The use of these transistors hardens the cell to tolerate a single event with a multiple-node upset at a large value of critical charge. Extensive simulation results are provided to assess TDICE with respect to traditional circuit figures of merit such as area, power consumption, and delay as well as PVT variations. The simulation results show that, at the expense of an increased area for the additional transistors, TDICE shows a nearly complete tolerance to a single event with a multiple-node upset.