Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset

Abstract

The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple node upset, i.e. a transient or soft fault affecting any two nodes in a cell. The proposed hardened memory cell utilizes a Schmitt trigger design; simulation shows that the multiple node upset tolerance is improved by nearly twice as much over existing designs. Moreover the 13T cell achieves a 33% reduction in write delay and only a 5% increase in power consumption compared to the DICE cell (consisting of 12 transistors). Simulation results are provided using the predictive technology file for 32nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple node upset tolerance of the proposed memory cell in the presence of process, voltage, and temperature variations in their designs.