Medium-scale Integrated Circuits Research Articles

A process for fabricating submicron all-refractory Josephson tunnel junction circuits

A process for fabricating submicron Josephson junctions suitable for integration in small- and medium-scale integrated circuits is described. This junction process utilizes a double-layer SiO/sub 2/ lift-off process in a cross-type geometry to define Josephson junctions. A photoresist strip with an arbitrary length and a fixed width defines the length of the junction. Its width is defined simultaneously with the metallization strip that crosses the first strip. The double-layer SiO/sub 2/ insures a pinhole-free oxide and yields excellent insulating properties suitable for medium-scale circuit applications. This process is used to fabricate Nb/AlO/sub x//Nb and NbN/MgO/NbN tunnel junctions as small as 0.5 mu m/sup 2/ with figures of merit (V/sub m/) larger than 30 mV. The repeatability of this process and its utility in high-current-density Josephson junction circuits are discussed.

Methodical aspects of logic synthesis

The increasing complexity of integrated circuits demands improved design quality. For system developments with small- or medium-scale integrated circuits, successive steps of the design process are interconnected loosely. Therefore, design checks, tests, and even redesigns could be performed without affecting large fractions of the overall design. With large scale integration (LSI) and especially very large scale integration (VLSI), the situation has changed drastically. The technological capability of these techniques allows designers to put a whole digital system on a few chips or even on one single chip. Consequently, all design steps between the definition of the system and its realization as a semiconductor structure must be strongly interconnected to yield successful and economic solutions. Reduced possibilities for testing and correcting design errors do not permit design concepts that follow the principle of trial and error. But up to now, the so-called logic design has been dominated by manually generated solutions. Because of the inherent possibilities of misinterpretation of the design task or of local design errors, analytical tools like simulation have to demonstrate the correctness of a design. But the restricted model accuracy, incomplete sets of test data, and excessive request for computing time are limiting factors of this design strategy in the context of VLSI. Therefore, other concepts for logic design are necessary that avoid analytical tools as much as possible but support the design process by synthesis. This paper discusses some methodical aspects of this problem, and it mentions some properties of logic design tools that are of practical importance.

SLIP: symbolic layout of integrated circuits with compaction

SLIP (symbolic layout interpreted for polycells) is a program which uses symbolic layout information to generate NMOS polycells (standard cells) for small-scale and medium-scale integrated circuits. At the input level, the designer works with symbolic nodes and lines representing transistors, loads, interlayer contacts and connections. The relative locations of the nodes and lines are then used to generate a hard-coordinate mask description. The mask description is generated by first translating the relative location information of the symbolic layout into an initial legal mask layout. The mask layout is then compacted using a shear-line compaction technique. The program is written in the C programming language and is currentky running on a Hewlett-Packard 21 MX minicomputer.

Reliability of MOS LSl circuits

MOS LSI circuits share many of the reliability problem associated with discrete semiconductors and medium-scale integrated circuits. However, because of the added complexity, larger chip size, and higher densities of MOS LSI circuits, different approaches are needed. A close working relationship between the designer, manufacturer, and user-the reliability triangle--is needed to generate the manufacturing controls, testing methods, and reliability assessment procedures and to optimize the performance and reliability of the MOS LSI circuits. Using this approach, the MOS LSI circuit, having more functions per external connection, can provide a more reliable system than one of equal complexity, based on discrete devices or less complex integrated circuits. Specific areas of reliability such as pattern sensitivity, manufacturing controls, assembly, packaging, and electrical testing have also been discussed.

MSI Testing at Dose Rates from 109 to 1012 RAD (S1)/S

A group of seven different types of medium scale integrated circuits (MSI) were tested at dose rates from 109 to 1012 Rad (Si)/s. These included five types of bipolar circuits and two types of MOS circuits. Catastrophic failures were encountered in two types of bipolar circuits and one type of MOS circuit. Radiation response of all circuits is described in the following paper.

R70-5 The Effect of IC's on the Design of Analog Computers

This paper reviews the impact of solid-state technology on the design and implementation of analog computers. Eight figures show the effects of transistors and medium-scale integrated circuits in the various phases of computer development. Basically, the use of integrated circuits is divided into two areas: logic and linear. Logic, or digital, circuits have been used for the control and address selection in the analog computer. Contrary to the author's claim that electromechanical devices used in the 1958 vintage machines were reliable with proper maintenance, transistor control logic was introduced specifically to improve the reliability and speed of the analog computer. (I do not believe that anyone who had to maintain stepping switches would disagree with me.) The introduction of patchable logic combined with the transistor control logic was a big step forward in increasing flexibility for the computer operator. As integrated circuits became practical from the viewpoint of cost per function, the control and patchable logic changed over to integrated circuits with additional features and flexibility.

A Digital Frequency Synthesizer for an AM and FM Receiver

This paper describes the design of a relatively economical, single crystal, frequency synthesizer that generates the required local oscillator frequencies for an AM and FM broadcast receiver. Selection of a station is accomplished by positioning switches to indicate the station's frequency. Fine tuning is not necessary. The receiver will not (for all practical purposes) drift, because the local oscillator frequency is crystal controlled. Low cost medium scale integrated circuits (MSI) are the building block of this synthesizer.