Methodical aspects of logic synthesis

Abstract

The increasing complexity of integrated circuits demands improved design quality. For system developments with small- or medium-scale integrated circuits, successive steps of the design process are interconnected loosely. Therefore, design checks, tests, and even redesigns could be performed without affecting large fractions of the overall design. With large scale integration (LSI) and especially very large scale integration (VLSI), the situation has changed drastically. The technological capability of these techniques allows designers to put a whole digital system on a few chips or even on one single chip. Consequently, all design steps between the definition of the system and its realization as a semiconductor structure must be strongly interconnected to yield successful and economic solutions. Reduced possibilities for testing and correcting design errors do not permit design concepts that follow the principle of trial and error. But up to now, the so-called logic design has been dominated by manually generated solutions. Because of the inherent possibilities of misinterpretation of the design task or of local design errors, analytical tools like simulation have to demonstrate the correctness of a design. But the restricted model accuracy, incomplete sets of test data, and excessive request for computing time are limiting factors of this design strategy in the context of VLSI. Therefore, other concepts for logic design are necessary that avoid analytical tools as much as possible but support the design process by synthesis. This paper discusses some methodical aspects of this problem, and it mentions some properties of logic design tools that are of practical importance.