VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

Abstract

Very large scale integration (VLSI) circuit comprises of integrated circuit (IC) with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiab ility (2-SAT) and 3Satisfiability (3-SAT) clauses in order to suit with the transistor configuration in VLSI circuit. In addit ion, we developed VLSI circu it based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for train ing, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circu its (HNN-2SAT and HNN-3SAT circuit ) developed by proposed design are better than the conventional circu it due to the early erro r detection in our circuit.