Memory-efficient circuits and architectures for asynchronous neuromorphic systems

Abstract

Highly parallel computing architectures inspired by the brain are attractive paradigms for performing tasks that require a high density of computation and memory. The ability to solve different complex computational problems within this domain requires the development of architectures that have both reconfigurability property and large amount of memory. However, one of the key problems is to understand how to trade-off between reconfigurability and memory resources in a systematic way. The state of the art large-scale neuromorphic systems usually sacrifice flexibility and reconfigurability to achieve scalable architectures with ad-hoc solutions. The main objective of this work is to develop a framework for systematically optimizing the trade-off between memory requirement and flexibility at both system and circuit levels. To this end, a novel design of event-driven neuromorphic circuits that utilizes the hardware resources efficiently at the “single-core” architecture level and a novel memory-efficient asynchronous routing method for reconfiguring the connectivity between neural processing cores are proposed. Specifically, I designed and fabricated mixed-signal Very Large Scale Integration (VLSI) circuits comprising biologically inspired silicon synapses/neurons and an on-chip asynchronous Static Random Access Memory (SRAM) for storing synaptic weights in a way that optimizes the memory usage for the implementation. The fabricated VLSI device is an evolution of existing neuromorphic architectures that enables more complex networks and learning behaviors. I devised a routing method that allows to flexibly choose the trade-offs between neural network configuration and routing memory requirements. The routing method is then optimized in terms of the memory needed to implement common and anatomically realistic neural network topologies. A library of asynchronous circuits is designed for implementing different routing schemes in VLSI. Finally, I demonstrate the full functionality of this approach by presenting experimental results acquired from the neuromorphic system with programmable synaptic weights and showing the scalability of the devised routing method analytically. The results of this thesis offer a route towards optimal design of large-scale neuromorphic systems using hybrid analog/digital VLSI circuits and memory efficient routing schemes.