Abstract
SLIP (symbolic layout interpreted for polycells) is a program which uses symbolic layout information to generate NMOS polycells (standard cells) for small-scale and medium-scale integrated circuits. At the input level, the designer works with symbolic nodes and lines representing transistors, loads, interlayer contacts and connections. The relative locations of the nodes and lines are then used to generate a hard-coordinate mask description. The mask description is generated by first translating the relative location information of the symbolic layout into an initial legal mask layout. The mask layout is then compacted using a shear-line compaction technique. The program is written in the C programming language and is currentky running on a Hewlett-Packard 21 MX minicomputer.
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