Measured Peak Output Research Articles

A 52–65 GHz Frequency Quadrupler With Low Conversion Loss and High Harmonic Rejection Ratio in 28-nm CMOS

This brief presents a 52-65 GHz frequency quadrupler with low conversion loss and high harmonic rejection ratio based on 28-nm bulk CMOS process. The frequency quadrupler includes two stages balanced frequency push-push doublers (PPD) cascaded with common-gate buffers. A series LC pair is placed between the PPD and the buffer of the first stage, which not only improves the conversion gain, but also suppresses the unwanted fundamental signals. A filter-integrated matching network is designed as the output matching network to reject undesired harmonics. As a result, the proposed design exhibits advantages in conversion gain and harmonic rejection ratio. The measured peak output power is -1.8 dBm and the output power 3-dB bandwidth is 52-65 GHz when the input power is 0 dBm. The even and odd harmonics rejection ratios are better than 35 dBc and 45 dBc, respectively, which can be used in high-performance mm-Wave LO chain.

A 272–341-GHz Integrated Amplifier-Frequency-Doubler Chain in 65-nm CMOS

This letter presents the development of a wideband amplifier-frequency-doubler chain (AFDC) operating at around 300 GHz based on a 65-nm CMOS technology. A new output matching technique for the frequency doubler (FD) is proposed, which provides extensively improved bandwidth and output power compared to a conventional approach often used. In addition, a five-stage transformer-based differential power amplifier has been developed that precedes the FD for sufficient input power and improved overall conversion gain. The integrated AFDC exhibited a measured peak output power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.0 dBm along with a 3-dB bandwidth of 69 GHz (272–341 GHz) or a fractional bandwidth of 22%. The measured peak conversion gain is 3.8 dB and the power consumption is 159.6 mW. The chip size is 660 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 155 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m excluding probing pads.

A SiGe BiCMOS Amplifier-Frequency Doubler Chain Operating for 284–328 GHz

This work describes the development of an amplifier frequency doubler chain (AFDC) operating at around 300 GHz based on SiGe BiCMOS technology. The driver amplifier is based on the differential cascode configuration, which employs coupled-line transformers for compact design. The frequency doubler is based on the class-B topology, which is known for exhibiting a large output power with low DC power consumption. The integrated AFDC, which consists of the frequency doubler and the preceding driver amplifier, exhibited a measured peak output power and DC-to-RF efficiency of -0.9 dBm and 0.97%, respectively, along with a conversion gain of -0.1 dB. It operates from 284 to 328 GHz with a 0-dBm input signal, consuming a total DC power of only 84 mW. The chip size is 720 × 310 μm2, excluding RF and DC pads.

A 300-GHz Transmitter Front End With −4.1-dBm Peak Output Power for Sub-THz Communication Using 130-nm SiGe BiCMOS Technology

This article presents a compact 300-GHz transmitter front end manufactured in a 130-nm SiGe BiCMOS process. The transmitter consists of a 240-GHz amplifier multiplier chain (AMC) and a modified 300-GHz Gilbert mixer. Limited by the space between top two thick metal layers of the SiGe process, the coupling coefficient between the coils, which form a transformer-based balun, is usually small at subterahertz (THz). Therefore, the vertical or horizontal coupling single-turn transformer-based balun will exhibit large insertion loss at around 300 GHz. In this work, a self-shielded Marchand balun (SSMB) with an enhancement to the coupling coefficient is proposed, which is realized by a novel multilayer metal topology with self-shielded coupling (SSC). The AMC is composed of a 120-GHz frequency doubler, a 120-GHz two-stage power amplifier (PA), and a two-way power synthesis balanced frequency doubler. This AMC exhibits a measured peak output power of 5.5 dBm at 252 GHz, with 48-GHz 3-dB bandwidth from 212 to 260 GHz. The transmitter chip achieves a maximum output power of −4.1 dBm at 300 GHz and delivers an output power better than −10 dBm from 270 to 315 GHz. Over the 30-GHz 3-dB bandwidth from 280 to 310 GHz, the transmitter shows a maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of −6.5 dBm at 296 GHz, a peak conversion gain of −11.2 dB at 298 GHz, and a local oscillator (LO)-to-RF leakage rejection better than 40 dB, with only 300-mW dc power consumption. Compared with other state of the arts, the transmitter exhibits a comparable output power among silicon-based transmitters near 300 GHz.

An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS

This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An $8\times $ analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

A 10-W X-Band Class-F High-Power Amplifier in a 0.25-μm GaAs pHEMT Technology

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and 3f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to provide 39-40-dBm output power. The class-F HPA achieves a 10-W output power and a peak power added efficiency (PAE) of 63% for pulsed-mode operation with a pulse repetition frequency (PRF) of 1 kHz and a duty cycle of 10%. The measured peak output power and PAE in the continuous-wave (CW) operation are 9.3 W and 58%, respectively.

X-band BWO directly driven by a Marx generator

X-band Resonant Reflector (RR) based Backward Wave Oscillators (BWO) has been designed and tested on a Marx generator. Output power dependence on the Resonant Reflector-BWO separation as well as on the applied magnetic field has been investigated using particle-in-cell (PIC) simulation. It was observed that the output power gets maximized for 3.0 T guiding magnetic field. The PIC simulation predicted BWO frequency as 9.22 GHz. BWO is operated on a Marx generator with peak diode voltage of 400 kV, and 4.0 kA as peak current. Microwave power was measured by D-dot probe placed in the far field region of the transmitting antenna. The measured peak output power was 120 MW at 9.35 GHz frequency for 0.7 T guiding magnetic field. At high magnetic field of 3.0 T the BWO peak power increased to 350 MW, however the frequency reduces to 9.25 GHz.

A 273.5–312-GHz Signal Source With 2.3 dBm Peak Output Power in a 130-nm SiGe BiCMOS Process

This article presents a 300-GHz signal source that consists of a 75-GHz voltage controlled oscillator (VCO), a static frequency divider-by-two circuit, a 150-GHz doubler, a 150-GHz power amplifier, and a 300-GHz doubler in a commercial 130-nm SiGe BiCMOS process. To extend the frequency tuning range, a switched substrate shield variable base inductor is adopted in the 75-GHz VCO design. The output power of the 150-GHz power amplifier is enhanced by a proposed auxiliary inductor for adjusting the phase difference of the LC balun. Besides, through systematically analyzing the influences of the input power and the base bias voltage on the output power, the 300-GHz doubler has been carefully designed for maximizing the output power. The measured peak output power is 2.3 dBm at 286 GHz and the output power is higher than 0 dBm from 282 to 312 GHz. The output frequency can be tuned from 273.5 to 312 GHz. The phase noise is measured to be $-$ 88.5 dBc/Hz @ 1 MHz at 300 GHz and better than $-$ 85.5 dBc/Hz @ 1 MHz across the whole tuning range. The total chip area is 1.254 mm $^2$ and the whole dc power consumption is 435 mW, which results in 0.4% DC-to-RF efficiency. Compared with the state-of-the-art silicon-based signal source at around 300 GHz, this article achieves the highest output power, the best tuning range, and a comparable phase noise without on-chip or free-space power combining techniques.

108–316- and 220–290-GHz Ultrabroadband Distributed Frequency Doublers

An analysis and design of distributed frequency doublers is presented at millimeter-wave (mm-wave) frequencies, including the $D$ -, $G$ -, and $H$ -bands. The phase condition required for coherent output summation in the distributed multipliers is analyzed to maximize the output power and bandwidth. Based on the analysis, two mm-wave distributed frequency doublers are designed and experimentally demonstrated. The first doubler combines three unit cells in a distributed manner, while the insertion phase is equalized between the input and output artificial transmission lines (T-lines). A differential quasi-cascode structure is proposed for each unit cell, which enables the bandwidth extension and chip-size reduction. The differential doubler exhibits a measured peak output power and a conversion gain of 3.5 dBm and −2.5 dB, respectively, at the output frequency of 165 GHz. At 276 GHz, the output power and conversion gain are 1.6 dBm and −6.2 dB, respectively. The doubler maintains high output power above −5 dBm from 108 to 316 GHz, which covers almost the entire $D$ -, $G$ -, and $H$ -bands. The second doubler combines five single-ended cascode unit cells to improve the output power and conversion gain. A bandpass filter is employed at the output T-line for spurious signal suppression. The single-ended doubler shows a measured peak output and conversion gain of 5.5 dBm and 0.3 dB, respectively, at 240 GHz. The bandwidth for −5-dBm output is from 220 to 290 GHz. Both doublers occupy a small chip area of 0.23 and 0.27 mm2, respectively, including all probing pads.

A Milliwatt-Level 70–110 GHz Frequency Quadrupler With &gt;30 dBc Harmonic Rejection

This article presents a two-channel 70-110-GHz frequency quadrupler in the GF8HP 0.12-μm SiGe BiCMOS process. The ×4 frequency multiplication is based on cascaded frequency doublers with an interstage bandpass filter to reject undesired harmonics. The measured peak output power is -1.5 to 3 dBm at 70-110 GHz, with a worst case harmonic rejection ratio (HRR) of >30 dBc. The chip size is 1.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 240 mW for the two-channel operation. To the best of our knowledge, this article represents state-of-the-art in terms of bandwidth, output power, and excellent HRR. Application areas include mm-wave multi-channel, mm-wave network analyzers, and wideband sources for radar and imaging systems and reconfigurable E-band radios.

D-Band and G-Band High-Performance GaN Power Amplifier MMICs

In this article, we present a set of gallium nitride (GaN) power amplifiers (PAs) that provide state-of-the-art performance within the D-band (110–170 GHz) and G-band (140–220 GHz) frequencies. A four-stage cascode PA operates with more than 25 dB of small-signal gain over a 107–148-GHz band. At 120 GHz, it can deliver up to 26.4 dBm of output power and up to 16.5% of power-added efficiency (PAE) with more than 26 dB of gain at saturation. The combination of these parameters is among the best reported with a solid-state technology at such high frequencies. The two G-band circuits are able to provide up to 40 GHz of 3-dB bandwidth and gain exceeding 10 dB up to 190 GHz. The measured peak output power is 15.8 dBm at 181 GHz in 0.6-dB gain compression with a corresponding PAE of 2.4%. To the best of our knowledge, these amplifiers show the highest gain above 170 GHz and the highest output power above 150 GHz among any reported GaN-based MMICs.

A Three-Stage 18.5–24-GHz GaN-on-SiC 4 W 40% Efficient MMIC PA

This paper presents the design and measured continuous-wave (CW) performance of a three-stage $K$ -band monolithic microwave integrated circuit (MMIC) power amplifier (PA) implemented in a 150-nm GaN-on-SiC process. The transistor peripheries are staged at a ratio of 1:2:8, and the output stage consists of two reactively combined $8 \times 100~\mu \text{m}$ HEMTs with individual source vias. The measured peak output power is greater than 4 W with peak power added efficiency (PAE) of greater than 40%. The output power exceeds 3.2 W over the frequency range of 18–24 GHz with less than 1.5-dB variation. The three-stage architecture enables greater than 20 dB of saturated gain from 18.5 to 24 GHz. The bandwidth, output power, and efficiency performance are investigated as a function of output stage drain voltage. A statistical analysis for 230 die fabricated on five wafers is presented, and eight MMICs are mounted and characterized over power and frequency.

Efficient Linear Millimeter-Wave Distributed Transceivers in CMOS SOI

Two $K_{u}$ - to V-band distributed amplifiers (DAs) based on nMOS and nMOS/pMOS gain stages and a distributed transceiver front end (DTFE) are presented for ultra-wideband power and low-noise amplification in a 45-nm RF CMOS silicon-on-insulator (SOI) technology. Supply scaling of gain stages through high-pass filter sections achieves high efficiency while maintaining a broadband 50- $\Omega $ match. The nMOS DA has a gain of 13 dB over a 3-dB bandwidth of 10–82 GHz and a minimum noise figure (NF) of 5.3 dB. The measured peak output power is 17.2 dBm with a peak power-added efficiency (PAE) of 17.4% at 50 GHz. The hybrid DA allows higher operating voltage and distortion cancelation of scaled pMOS devices to an achieve output power of 17.5 dBm with PAE of 20.2% and low third-order intermodulation and amplitude–phase nonlinearities. The DTFE utilizes time-domain duplexing to drive a shared antenna port for transmit (TX) and receive (RX) modes. It achieves TX gain of 11.7 dB from 12–76 GHz with peak output power of 17 dBm and PAE of 14.2%. RX gain is 9 dB from 11–77 GHz with a minimum NF of 6.2 dB. The 5-GHz wideband 16-QAM is demonstrated in the amplifier circuits for data rates exceeding 20 Gb/s.

Design of a Compact GaN MMIC Doherty Power Amplifier and System Level Analysis With X-Parameters for 5G Communications

This paper presents a monolithic microwave integrated circuit Doherty power amplifier (DPA) operating at sub-6 GHz for 5G communication applications by a 0.25- $\mu \text{m}$ gallium nitride high-electron mobility transistor process. A compact impedance inverter and output matching of the DPA are achieved using a transmission line network and shunt capacitors. Also, the size ratio of power cells in the main and auxiliary amplifiers is optimized for a high efficiency at output power backoff (OPBO). The measured peak output power ( ${P}_{\text {out}}$ ) and the 1-dB compression point ( ${P}_{{1\,\text {dB}}}$ ) are 38.7 and 32.1 dBm, respectively, at 5.9 GHz. The power-added efficiency at 6-dB OPBO is up to 49.5%. Without digital predistortion (DPD), the DPA can deliver an average ${P}_{\text {out}}$ of 23.5 dBm with error vector magnitude (EVM) <−28 dB and 21.5 dBm with EVM <−32 dB for 64-quadrature amplitude modulation (QAM) and 256-QAM signals, respectively. The measured X-parameters are employed to further investigate the DPA nonlinear characteristics and verify the accuracy of conventionally used power amplifier characterization/measurement methods for system-level design and testing applications. The simulated results based on the X-parameters also indicate that the average output power can be enhanced up to 25.7 dBm with DPD for 256-QAM.

A −2.5-dBm, 5.1%-Tuning-Range, 417-GHz Signal Source With Gate-to-Drain-Coupled Oscillator in 65-nm CMOS Process

This letter presents a novel subterahertz CMOS signal source with high output power. The proposed oscillators are mutually injected to align their frequencies and phases through a transformer that couples the gate and drain signals between the adjacent cores. The proposed architecture is implemented using the 65-nm CMOS technology. The measured peak output power is −2.5 dBm at 417 GHz while dissipating 108 mW. The proposed signal source shows the highest dc-to-RF efficiency (0.5%) and a wide tuning range (5.1%) among state-of-the-art signal sources above 400 GHz.

An 88-GHz Compact Fundamental Oscillator With 19.4% DC-to-RF Efficiency and 7.5-dBm Output Power in 130-nm SiGe BiCMOS

This letter presents an 88-GHz fundamental oscillator. By utilizing a device-centric design technique as well as the self-feeding oscillator topology, the fundamental power generation is optimized. The circuit is fabricated in 130-nm SiGe BiCMOS technology and occupies only $200 \times 140\,\,\mu \text{m}^{\mathbf {2}}$ area. The oscillator achieves 7.5 dBm of measured peak output power and 19.4% DC-to-RF efficiency. The output frequency is tunable from 87.5 GHz to 88.5 GHz. The measured phase noise is −107 dBc/Hz at 1 MHz offset corresponding to a phase noise figure-of-merit of 191.1 at this offset frequency. To the best of our knowledge, this oscillator exhibits the highest reported DC-to-RF efficiency among Si/SiGe mm-wave oscillators at this frequency range.

A 91-GHz Fundamental VCO With 6.1% DC-to-RF Efficiency and 4.5 dBm Output Power in 0.13-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS

In this letter, we present a systematic method for designing high-efficiency, high-power millimeter wave oscillators. This method effectively manipulates the dc current of the drain of the core transistors to minimize the time during which the transistor is on. Furthermore, an additional capacitor at the source of the transistor assists lowering the power consumption while maintaining the same fundamental generated power. To show the feasibility of this method, a class-E-type oscillator architecture is implemented in a 0.13-μm CMOS technology (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> = 116 GHz). The proposed voltage-controlled oscillator (VCO) achieves the record DC-to-RF efficiency of 6.1% at a center frequency of 91 GHz (~0.8*f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) on CMOS. The measured peak output power is 4.5 dBm while the VCO consumes 46 mW of dc power and features a figure of merit of -169.6 dBc/Hz at 1-MHz offset frequency. The fabricated VCO occupies 0.51 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area including the pads.

A 270 GHz × 9 Multiplier Chain MMIC With On-Chip Dielectric-Resonator Antenna

This paper presents a 270 GHz × 9 multiplier chain with on-chip dielectric-resonator antenna (DRA) developed in a commercial 0.1- μ m GaAs pseudomorphic high electron-mobility transistor technology with cutoff frequencies $f_{{\rm{T}}}\, / f_{{\rm{MAX}}}$ of 130/180 GHz. The multiplier integrates a W-band tripler followed by a driver amplifier, a J-band tripler, and an on-chip antenna. The multiplier breakout achieves a measured peak output power of –4 dBm at 270 GHz and a 3-dB bandwidth of 40 GHz (from 255 to 295 GHz). By introducing the high-pass matching network into the multiplier design, the in-band unwanted harmonic suppression is improved to be over 40 dBc within the entire bandwidth. The higher order mode (TE δ 13 mode) dielectric resonator is introduced in the on-chip antenna design to enhance the antenna gain and bandwidth without additional chip area consumption. The multiplier chain with the on-chip DRA has a measured EIRP of +2 dBm at 270 GHz and a 3-dB bandwidth of 33 GHz (from 258 to 291 GHz). Compared with other J-band multipliers, this paper achieves the best spurious suppression and comparable output power while using the technology with the lowest cutoff frequencies.

High output power 243 GHz voltage controlled oscillator in a 130 nm SiGe BiCMOS process

A four-stage fundamental ring oscillator based on 130 nm SiGe HBT technology is reported. By utilising a novel ground wall decoupling structure as well as a step impedance conversion structure, the generated output power is optimised. The fundamental VCO has a measured peak output power of −1.4 dBm at 243 GHz. The output frequency could be tuned from 237.2 to 249.8 GHz with a tuning range of 5.18%. The core size of the oscillator is only 40 × 80 μm2. The peak DC-to-RF efficiency is 1.95% at a 0.94 V power supply. To the best of our knowledge, the proposed VCO achieves the highest output power compared with the other silicon-based fundamental oscillators over 200 GHz.

A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.