Abstract
This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An $8\times $ analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.
Highlights
W IRELESS systems in high data-rate applications are increasingly required to support a wide signal bandwidth and complex modulation schemes, which usually feature high peak-to-average power ratio (PAPR)
To design a class-E radio-frequency digital-to-analog converter (RFDAC) with an improved drain efficiency, a transformer-based matching network can be considered with the following features: 1) the matching-network transformer has multiple primary coils and one secondary coil, which creates the possibility of varying the transformer’s turns-ratio by adding/reducing the number of primary coils; 2) different groups of switches connect with different primary coils, which provides the chance that the turns-ratio can be controlled by the input data; 3) the value of individual inductance and capacitance, depending on their roles in the matching network, still meets the requirement of class-E operational principle
The chip can read the data from the memories through Field Programmable Gate Array (FPGA) Mezzanine Card (FMC) connectors
Summary
W IRELESS systems in high data-rate applications are increasingly required to support a wide signal bandwidth and complex modulation schemes, which usually feature high peak-to-average power ratio (PAPR). Reference [15] has exploited this methodology further in a Bluetooth low energy transceiver where active circuits are located underneath the transformers in both the DCO and DPA Both of these designs deliver very limited RF power. Matching network on-chip and they deliver maximum output power as high as 14.6 dBm, 16.8 dBm, 22.8 dBm, 20.5 dBm and 13.5 dBm, respectively In those designs, the active circuitry and the passive matching network components occupy separate locations on the floor plan, with the matching network occupying almost the same area as the DPA array. A fully integrated Cartesian RFDAC is proposed in this paper The design of this RFDAC demonstrates three innovations: 1) Active devices are placed underneath the impedance-transformation matching network, while delivering >17 dBm of RF output power.
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