A 270 GHz × 9 Multiplier Chain MMIC With On-Chip Dielectric-Resonator Antenna

Abstract

This paper presents a 270 GHz × 9 multiplier chain with on-chip dielectric-resonator antenna (DRA) developed in a commercial 0.1- μ m GaAs pseudomorphic high electron-mobility transistor technology with cutoff frequencies $f_{{\rm{T}}}\, / f_{{\rm{MAX}}}$ of 130/180 GHz. The multiplier integrates a W-band tripler followed by a driver amplifier, a J-band tripler, and an on-chip antenna. The multiplier breakout achieves a measured peak output power of –4 dBm at 270 GHz and a 3-dB bandwidth of 40 GHz (from 255 to 295 GHz). By introducing the high-pass matching network into the multiplier design, the in-band unwanted harmonic suppression is improved to be over 40 dBc within the entire bandwidth. The higher order mode (TE δ 13 mode) dielectric resonator is introduced in the on-chip antenna design to enhance the antenna gain and bandwidth without additional chip area consumption. The multiplier chain with the on-chip DRA has a measured EIRP of +2 dBm at 270 GHz and a 3-dB bandwidth of 33 GHz (from 258 to 291 GHz). Compared with other J-band multipliers, this paper achieves the best spurious suppression and comparable output power while using the technology with the lowest cutoff frequencies.